From: zyw@rock-chips•com (Chris Zhong)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration
Date: Tue, 24 Jan 2017 10:42:17 +0800 [thread overview]
Message-ID: <5886BF09.6090301@rock-chips.com> (raw)
In-Reply-To: <20170123124925.4fa10fc2.john@metanate.com>
On 01/23/2017 08:49 PM, John Keeping wrote:
> Hi Chris,
>
> On Mon, 23 Jan 2017 09:38:54 +0800, Chris Zhong wrote:
>> On 01/22/2017 12:31 AM, John Keeping wrote:
>>> The multiplication ratio for the PLL is required to be even due to the
>>> use of a "by 2 pre-scaler". Currently we are likely to end up with an
>>> odd multiplier even though there is an equivalent set of parameters with
>>> an even multiplier.
>>>
>>> For example, using the 324MHz bit rate with a reference clock of 24MHz
>>> we end up with M = 27, N = 2 whereas the example in the PHY databook
>>> gives M = 54, N = 4 for this bit rate and reference clock.
>>>
>>> By walking down through the available multiplier instead of up we are
>>> more likely to hit an even multiplier. With the above example we do now
>>> get M = 54, N = 4 as given by the databook.
>>>
>>> While doing this, change the loop limits to encode the actual limits on
>>> the divisor, which are:
>>>
>>> 40MHz >= (pllref / N) >= 5MHz
>> This formula is limit for N, but we still can not guarantee to get an
>> even M.
>> Do you think we should do a check for M.
>> such as:
>> if (m % 2)
>> continue;
>> ...
>> for (i = pllref / 5; i > (pllref / 40); i--) {
>> pre = pllref / i;
>> if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
>> tmp = target_mbps % pre;
>> n = i;
>> m = target_mbps / pre;
>> if (m % 2)
>> continue;
>> }
>> if (tmp == 0)
>> break;
>> }
>>
>> if (m % 2)
>> m++;
>>
>> dsi->lane_mbps = pllref / n * m;
>> dsi->input_div = n;
>> dsi->feedback_div = m;
> Yes, I agree that there should be a check for M, but I'm not sure if
> the version above is sufficient. The "m % 2" check inside the loop
> means that we don't break immediately when tmp=0 but then we are
> guaranteed to break next time without having modified n, m because now
> tmp=0 so "tmp > (target_mbps % pre)" is always false and we just hit the
> "if (tmp == 0) break" case next time.
>
> Given that the descending loop already means that if we can hit "tmp"
> exactly we are more likely to do so with a bigger N and even M, I think
> it might be better to just fix M after the loop like:
>
> if (m % 2) {
> if (m < 256 && (n * 2) <= (pllref / 5)) {
> n *= 2;
> m *= 2;
> } else {
> m++;
> }
> }
>
> but I haven't thought about this too carefully.
>
> For this series, I'd rather either keep this patch as it is or drop it
> in favour of a more comprehensive solution. I don't want to block the
> other fixes waiting for a perfect fix here and we can always improve
> this further with a follow-up patch.
Agree, We can improve the whole formula in the future.
>
>>> Signed-off-by: John Keeping <john@metanate•com>
>>> ---
>>> Unchanged in v2
>>> ---
>>> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>>> index 12432e41971b..f2320cf1366c 100644
>>> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>>> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>>> @@ -519,7 +519,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>>> pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
>>> tmp = pllref;
>>>
>>> - for (i = 1; i < 6; i++) {
>>> + for (i = pllref / 5; i > (pllref / 40); i--) {
>>> pre = pllref / i;
>>> if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
>>> tmp = target_mbps % pre;
>>
>
>
next prev parent reply other threads:[~2017-01-24 2:42 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-21 16:31 [PATCH v2 00/26] drm/rockchip: MIPI fixes & improvements John Keeping
2017-01-21 16:31 ` [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping
2017-01-22 3:58 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 02/26] drm/rockchip: dw-mipi-dsi: rename commit hook to enable John Keeping
2017-01-21 16:31 ` [PATCH v2 03/26] drm/rockchip: dw-mipi-dsi: pass mode in where needed John Keeping
2017-01-22 4:00 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping
2017-01-22 6:08 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 05/26] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping
2017-01-21 16:31 ` [PATCH v2 06/26] drm/rockchip: dw-mipi-dsi: fix generic packet status check John Keeping
2017-01-22 6:24 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf John Keeping
2017-01-22 6:42 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping
2017-01-22 6:44 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 09/26] drm/rockchip: dw-mipi-dsi: respect message flags John Keeping
2017-01-22 7:14 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 10/26] drm/rockchip: dw-mipi-dsi: only request HS clock when required John Keeping
2017-01-22 8:10 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 11/26] drm/rockchip: dw-mipi-dsi: don't assume buffer is aligned John Keeping
2017-01-22 8:16 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 12/26] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping
2017-01-22 8:22 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 13/26] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable John Keeping
2017-01-22 8:37 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping
2017-01-22 9:37 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset John Keeping
2017-01-22 9:37 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 16/26] drm/rockchip: dw-mipi-dsi: configure bias and bandgap before enable John Keeping
2017-01-21 16:31 ` [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured John Keeping
2017-01-22 10:07 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing John Keeping
2017-01-22 3:06 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration John Keeping
2017-01-23 1:38 ` Chris Zhong
2017-01-23 12:49 ` John Keeping
2017-01-24 2:42 ` Chris Zhong [this message]
2017-01-21 16:31 ` [PATCH v2 20/26] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping
2017-01-23 0:49 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 21/26] drm/rockchip: dw-mipi-dsi: use positive check for N{H, V}SYNC John Keeping
2017-01-21 16:31 ` [PATCH v2 22/26] drm/rockchip: vop: test for P{H,V}SYNC John Keeping
2017-01-23 7:12 ` Mark yao
2017-01-21 16:31 ` [PATCH v2 23/26] drm/rockchip: dw-mipi-dsi: defer probe if panel is not loaded John Keeping
2017-01-21 16:31 ` [PATCH v2 24/26] drm/rockchip: dw-mipi-dsi: support non-burst modes John Keeping
2017-01-23 6:11 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control John Keeping
2017-01-23 6:12 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 26/26] drm/rockchip: dw-mipi-dsi: support read commands John Keeping
2017-01-22 3:08 ` Chris Zhong
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