From: Will Deacon <will@kernel•org>
To: Nicolin Chen <nicolinc@nvidia•com>
Cc: Ashish Mhetre <amhetre@nvidia•com>,
robin.murphy@arm•com, joro@8bytes•org, jgg@ziepe•ca,
linux-arm-kernel@lists•infradead.org, iommu@lists•linux.dev,
linux-kernel@vger•kernel.org, linux-tegra@vger•kernel.org
Subject: Re: [PATCH v3 2/3] iommu/arm-smmu-v3: Detect Tegra264 erratum
Date: Tue, 2 Jun 2026 21:59:39 +0100 [thread overview]
Message-ID: <ah9EO-djR3Tf9ohf@willie-the-truck> (raw)
In-Reply-To: <ah89vg26255v4lqF@Asurada-Nvidia>
On Tue, Jun 02, 2026 at 01:31:58PM -0700, Nicolin Chen wrote:
> On Tue, Jun 02, 2026 at 09:13:39PM +0100, Will Deacon wrote:
> > On Mon, Jun 01, 2026 at 10:48:44AM +0000, Ashish Mhetre wrote:
> > > Tegra264 SMMU is affected by erratum where a TLB entry can survive an
> > > invalidation that races with concurrent traffic targeting the same
> > > entry. The hardware-recommended software workaround is to issue every
> > > CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue
> > > is guaranteed to evict the entry. ATC_INV is not affected and must not
> > > be doubled.
> > >
> > > The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it
> > > cannot be detected from hardware ID. Tegra264 boots from device tree
> > > only and has no ACPI/IORT support, so detection is through device
> > > tree only.
> >
> > That seems odd to me -- whether the hardware has the erratum is
> > completely unrelated to whether it probes using DT or ACPI, so I find it
> > really weird to have the workaround enabled when booting with DT and not
> > when booting with ACPI. We should have consistent behaviour between the
> > two.
>
> That's a good point. Yet, for ACPI to detect the erratum, we would
> need a new IORT model or flag, right? That would need to go through
> the entire ACPI protocol to update SMMU's IORT spec and the header
> accordingly, which we don't have a use case to do so or to test it.
>
> What would you like us to do here for the consistency?
Gah, I now realise I've mixed up Tegra264 and Tegra241 because
tegra_cmdqv_dt_probe() is only called if the compatible string matches
"nvidia,tegra264-smmu" yet all the cmdqv stuff talks only about
Tegra241. So I was surprised that the ACPI probing code for Tegra241
wasn't enabling the workaround.
But if you're saying that:
1. Tegra264 never uses ACPI
2. Tegra241 doesn't have the invalidation erratum
Then I'm less worried (even though it's a shame that we can't detect
the erratum from the hardware itself).
Will
next prev parent reply other threads:[~2026-06-02 20:59 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-01 10:48 [PATCH v3 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Ashish Mhetre
2026-06-01 10:48 ` [PATCH v3 1/3] iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Ashish Mhetre
2026-06-02 19:55 ` Will Deacon
2026-06-02 20:08 ` Nicolin Chen
2026-06-02 20:23 ` Will Deacon
2026-06-01 10:48 ` [PATCH v3 2/3] iommu/arm-smmu-v3: Detect Tegra264 erratum Ashish Mhetre
2026-06-02 20:13 ` Will Deacon
2026-06-02 20:31 ` Nicolin Chen
2026-06-02 20:59 ` Will Deacon [this message]
2026-06-02 21:06 ` Nicolin Chen
2026-06-01 10:48 ` [PATCH v3 3/3] iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264 Ashish Mhetre
2026-06-01 18:37 ` Nicolin Chen
2026-06-02 20:22 ` Will Deacon
2026-06-02 20:35 ` Nicolin Chen
2026-06-03 0:59 ` Jason Gunthorpe
2026-06-03 1:01 ` Jason Gunthorpe
2026-06-03 11:33 ` Will Deacon
2026-06-02 16:31 ` [PATCH v3 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Mostafa Saleh
2026-06-02 18:23 ` Jason Gunthorpe
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