* [PATCH 0/1] add missing L2 cache properties for Meson8 and Meson8b
@ 2017-04-17 21:42 Martin Blumenstingl
2017-04-17 21:42 ` [PATCH 1/1] ARM: dts: meson: Extend L2 cache controller node " Martin Blumenstingl
0 siblings, 1 reply; 3+ messages in thread
From: Martin Blumenstingl @ 2017-04-17 21:42 UTC (permalink / raw)
To: linux-arm-kernel
This adds three missing L2 cache properties for the cache controller
on Meson8 and Meson8b.
This patch was originally written by Carlo Caione, I just took it and
applied it to Meson8 as well and rebased it.
This patch is based on my previous series from [0]: "Amlogic Meson (32-bit)
.dts cleanups"
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-April/003399.html
Carlo Caione (1):
ARM: dts: meson: Extend L2 cache controller node for Meson8 and
Meson8b
arch/arm/boot/dts/meson8.dtsi | 6 ++++++
arch/arm/boot/dts/meson8b.dtsi | 6 ++++++
2 files changed, 12 insertions(+)
--
2.12.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/1] ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8b
2017-04-17 21:42 [PATCH 0/1] add missing L2 cache properties for Meson8 and Meson8b Martin Blumenstingl
@ 2017-04-17 21:42 ` Martin Blumenstingl
2017-05-19 22:50 ` Kevin Hilman
0 siblings, 1 reply; 3+ messages in thread
From: Martin Blumenstingl @ 2017-04-17 21:42 UTC (permalink / raw)
To: linux-arm-kernel
From: Carlo Caione <carlo@endlessm•com>
This patch extends the L2 cache controller node for the Amlogic Meson8
and Meson8b SoCs with some missing parameters. These are taken from the
Amlogic GPL kernel source.
Signed-off-by: Carlo Caione <carlo@endlessm•com>
[apply the change to Meson8 and Meson8b and updated description]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail•com>
---
arch/arm/boot/dts/meson8.dtsi | 6 ++++++
arch/arm/boot/dts/meson8b.dtsi | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 5eaaf067c76a..6993077331c7 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -188,6 +188,12 @@
clocks = <&clk81>;
};
+&L2 {
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x100000 0xc0000000>;
+};
+
&spifc {
clocks = <&clk81>;
};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index ef9ac974111c..d9f116a418b2 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -171,6 +171,12 @@
};
};
+&L2 {
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x100000 0xc0000000>;
+};
+
&uart_AO {
clocks = <&clkc CLKID_CLK81>;
};
--
2.12.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 1/1] ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8b
2017-04-17 21:42 ` [PATCH 1/1] ARM: dts: meson: Extend L2 cache controller node " Martin Blumenstingl
@ 2017-05-19 22:50 ` Kevin Hilman
0 siblings, 0 replies; 3+ messages in thread
From: Kevin Hilman @ 2017-05-19 22:50 UTC (permalink / raw)
To: linux-arm-kernel
Martin Blumenstingl <martin.blumenstingl@googlemail•com> writes:
> From: Carlo Caione <carlo@endlessm•com>
>
> This patch extends the L2 cache controller node for the Amlogic Meson8
> and Meson8b SoCs with some missing parameters. These are taken from the
> Amlogic GPL kernel source.
>
> Signed-off-by: Carlo Caione <carlo@endlessm•com>
> [apply the change to Meson8 and Meson8b and updated description]
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail•com>
Applied to v4.13/dt64,
Thanks,
Kevin
^ permalink raw reply [flat|nested] 3+ messages in thread
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