From: Scott Wood <scottwood@freescale•com>
To: Po Liu <Po.Liu@freescale•com>
Cc: linuxppc-dev@ozlabs•org, Mingkai Hu <Mingkai.Hu@freescale•com>,
afleming@freescale•com, Po Liu <Po.Liu@freescale•com>
Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293
Date: Tue, 30 Jul 2013 13:28:11 -0500 [thread overview]
Message-ID: <1375208891.30721.74@snotra> (raw)
In-Reply-To: <1375174163-19246-2-git-send-email-Po.Liu@freescale.com> (from Po.Liu@freescale.com on Tue Jul 30 03:49:22 2013)
On 07/30/2013 03:49:22 AM, Po Liu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale•com>
>=20
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale•com>
> Signed-off-by: Po Liu <Po.Liu@freescale•com>
> ---
> Changes for v2:
> - None
> Changes for v3:
> - None
>=20
> arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193 =20
> +++++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/c293si-pre.dtsi | 63 ++++++++++
> 2 files changed, 256 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
>=20
> diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi =20
> b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> new file mode 100644
> index 0000000..bd20832
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> @@ -0,0 +1,193 @@
> +/*
> + * C293 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following =20
> conditions are met:
> + * * Redistributions of source code must retain the above =20
> copyright
> + * notice, this list of conditions and the following =20
> disclaimer.
> + * * Redistributions in binary form must reproduce the above =20
> copyright
> + * notice, this list of conditions and the following =20
> disclaimer in the
> + * documentation and/or other materials provided with the =20
> distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =20
> products
> + * derived from this software without specific prior written =20
> permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms =20
> of the
> + * GNU General Public License ("GPL") as published by the Free =20
> Software
> + * Foundation, either version 2 of that License or (at your option) =20
> any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' =20
> AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =20
> IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR =20
> PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =20
> FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR =20
> CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS =20
> OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =20
> CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT =20
> LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =20
> USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +&ifc {
> + #address-cells =3D <2>;
> + #size-cells =3D <1>;
> + compatible =3D "fsl,ifc", "simple-bus";
> + interrupts =3D <19 2 0 0>;
> +};
> +
> +/* controller at 0xa000 */
> +&pci0 {
> + compatible =3D "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
> + device_type =3D "pci";
> + #size-cells =3D <2>;
> + #address-cells =3D <3>;
> + bus-range =3D <0 255>;
> + clock-frequency =3D <33333333>;
> + interrupts =3D <16 2 0 0>;
Remove clock-frequency (surely PCIe is not running at 33 MHz).
> + crypto@80000 {
> +/include/ "qoriq-sec6.0-0.dtsi"
> + };
> +
> + crypto@80000 {
> + reg =3D <0x80000 0x20000>;
> + ranges =3D <0x0 0x80000 0x20000>;
> +
> + jr@1000{
> + interrupts =3D <45 2 0 0>;
> + };
> + jr@2000{
> + interrupts =3D <57 2 0 0>;
> + };
> + };
Do these inline the way the example shows.
-Scott=
next prev parent reply other threads:[~2013-07-30 18:28 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-25 1:54 [PATCH 1/4] powerpc/85xx: Add SEC6.0 device tree Po Liu
2013-04-25 1:54 ` [PATCH 2/4] powerpc/85xx: Add silicon device tree for C293 Po Liu
2013-04-25 1:54 ` [PATCH 3/4] powerpc/85xx: Add C293PCIE board support Po Liu
2013-07-22 22:58 ` [3/4] " Scott Wood
2013-07-23 7:47 ` Liu Po-B43644
2013-07-23 16:22 ` Scott Wood
2013-04-25 1:54 ` [PATCH 4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE Po Liu
2013-07-22 22:59 ` [4/4] " Scott Wood
2013-07-22 23:00 ` Scott Wood
2013-07-23 7:13 ` Liu Po-B43644
2013-07-26 2:41 ` [PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree Po Liu
2013-07-26 2:41 ` [PATCH v2 2/3] powerpc/85xx: Add silicon device tree for C293 Po Liu
2013-07-26 2:41 ` [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support Po Liu
2013-07-26 21:59 ` Scott Wood
2013-07-29 2:20 ` Liu Po-B43644
2013-07-29 18:10 ` Scott Wood
2013-07-30 8:49 ` [PATCH v3 1/3] powerpc/85xx: Add SEC6.0 device tree Po Liu
2013-07-30 8:49 ` [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293 Po Liu
2013-07-30 18:28 ` Scott Wood [this message]
2013-07-31 2:13 ` Liu Po-B43644
2013-07-31 15:46 ` Scott Wood
2013-08-01 2:32 ` Liu Po-B43644
2013-08-07 23:24 ` Scott Wood
2013-07-30 8:49 ` [PATCH v3 3/3] powerpc/85xx: Add C293PCIE board support Po Liu
2013-07-30 18:29 ` Scott Wood
2013-08-02 6:39 ` [PATCH v4 1/3] powerpc/85xx: Add SEC6.0 device tree Po Liu
2013-08-02 6:39 ` [PATCH v4 2/3] powerpc/85xx: Add silicon device tree for C293 Po Liu
2013-08-02 6:39 ` [PATCH v4 3/3] powerpc/85xx: Add C293PCIE board support Po Liu
2013-07-26 21:55 ` [PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree Scott Wood
2013-07-29 2:14 ` Liu Po-B43644
2013-07-22 22:41 ` [1/4] " Scott Wood
2013-07-23 8:01 ` Liu Po-B43644
2013-07-23 23:24 ` Scott Wood
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