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* LPC burst accesses
@ 2007-12-11  9:46 Kári Davíðsson
  2007-12-11 13:43 ` WITTROCK
  0 siblings, 1 reply; 3+ messages in thread
From: Kári Davíðsson @ 2007-12-11  9:46 UTC (permalink / raw)
  To: linuxppc-embedded

Hi,

I am in the process of optimizing read accesses to an FPGA in one of our =
custom mpc5200b boards.

I have attempted to do this in two ways, i.e.

1) With the the general SDMA task. Also used by the AC97 audio codec =
driver.
2) Trought the SCLPC fifo offered in relation with the LP bus.

The documentation on freescales site is somehow very vague and even =
though they talk about
read burst accesses they also seem not to be able to guarantee under =
what conditions
burst accesses are generated/not generated. The result that I am seeing =
is that even though=20
that the DMA task and fifo is working as expected (transfering data from =
the FPGA to memory/fifo)
burst reads are _never_ generated (short burst/long burst).

Is there any enlightened soul out there that might shed a litle light on =
this issue or point me into=20
the right direction where I can find more concrete documentation.

I am using linux 2.6.23 as base for these experiments.

rg
kd

^ permalink raw reply	[flat|nested] 3+ messages in thread

• * Re: LPC burst accesses
    2007-12-11  9:46 LPC burst accesses Kári Davíðsson
  @ 2007-12-11 13:43 ` WITTROCK
    2007-12-12 10:36   ` Kári Davíðsson
    0 siblings, 1 reply; 3+ messages in thread
  From: WITTROCK @ 2007-12-11 13:43 UTC (permalink / raw)
    To: linuxppc-embedded
  
  
  I remember doing something like this a while back.  I ended up not
  implementing it in my project for other reasons, but here is some
  correspondence I had with Freescale:
  
  
  The question
  ---------------------------------------------------------------------
  I am using the LocalPlus bus and BestComm on a MPC5200B to communicate with
  an external FPGA.
  
  I am currently using CS2 as the chip select for the FPGA.  If I configure
  the chip select 2 configuration register for a 16bit address width and 2
  byte bus width then all works well (MBAR + 0x0308 = 0x00003500).
  
  I am now trying to configure CS2 to operate in LargeFlash mode with 2 byte
  bus width and 26bit address (MBAR + 0x0308 = 0x00003D00) in order to support
  a burst read.  I have configured the Chip Select Burst Control Register
  (BRE2=1), and ensured that PCI is disabled, however I do not see a burst
  read performed on the bus.
  
  Before I investigate any further, should it be possible to use the LP in
  LargeFlash mode together with its assosciated FIFO and BestComm to perform a
  burst read?
  
  
  The Reply
  Local Plus controller performs burst read from LargeFlash or MostGraphic
  memory only if an XLB master (CPU) or SCLPC interface initiates burst
  access.
  
  In the case of CPU, you should enable cache for Local Plus memory.
  In the case of SCLPC, you should define BPT=8 in the SCLPC Control Register
  (MBAR + 0x3C08).
  
  Other configurations doesn't force bursting.
  
  Thank you for your interest in Freescale Semiconductor products and for the
  opportunity to serve you.
  Should you need to contact us with regard to this message, please see the
  notes below.
  
  I hope its of some use.
  
  -WITTROCK
  
  
  
  -- 
  View this message in context: http://www.nabble.com/LPC-burst-accesses-tp14270986p14274105.html
  Sent from the linuxppc-embedded mailing list archive at Nabble.com.
  
  ^ permalink raw reply	[flat|nested] 3+ messages in thread

• • * RE: LPC burst accesses
      2007-12-11 13:43 ` WITTROCK
    @ 2007-12-12 10:36   ` Kári Davíðsson
      0 siblings, 0 replies; 3+ messages in thread
    From: Kári Davíðsson @ 2007-12-12 10:36 UTC (permalink / raw)
      To: linuxppc-embedded; +Cc: WITTROCK
    
    Thanks,
    
    Using this configuration of the SCLPC I was able to get burst accesses.
    
    Getting bursts with the SDMA general purpose task (without the SCLPC =
    fifo) is
    still a mistery to me. I somehow have the feeling that with the CPU one =
    can only
    get bursts if we are capable of executing code out of the bank, which =
    implies=20
    multiplexed mode of the bank. Multiplexed mode I am not able to do, at =
    least
    not at this time.
    
    rg
    kd=20
    
    
    --=20
    K=E1ri Dav=ED=F0sson                   | kari.davidsson@marel•is
    Hugb=FAna=F0arger=F0                   | www.marel.com
    Tel: +354 563 8156 Fax: +354 563 8001
    Iceland
    
    -----Original Message-----
    From: linuxppc-embedded-bounces+karidav=3Dmarel.is@ozlabs•org =
    [mailto:linuxppc-embedded-bounces+karidav=3Dmarel.is@ozlabs•org] On =
    Behalf Of WITTROCK
    Sent: 11. desember 2007 13:43
    To: linuxppc-embedded@ozlabs•org
    Subject: Re: LPC burst accesses
    
    
    I remember doing something like this a while back.  I ended up not =
    implementing it in my project for other reasons, but here is some =
    correspondence I had with Freescale:
    
    
    The question
    ---------------------------------------------------------------------
    I am using the LocalPlus bus and BestComm on a MPC5200B to communicate =
    with an external FPGA.
    
    I am currently using CS2 as the chip select for the FPGA.  If I =
    configure the chip select 2 configuration register for a 16bit address =
    width and 2 byte bus width then all works well (MBAR + 0x0308 =3D =
    0x00003500).
    
    I am now trying to configure CS2 to operate in LargeFlash mode with 2 =
    byte bus width and 26bit address (MBAR + 0x0308 =3D 0x00003D00) in order =
    to support a burst read.  I have configured the Chip Select Burst =
    Control Register (BRE2=3D1), and ensured that PCI is disabled, however I =
    do not see a burst read performed on the bus.
    
    Before I investigate any further, should it be possible to use the LP in =
    LargeFlash mode together with its assosciated FIFO and BestComm to =
    perform a burst read?
    
    
    The Reply
    Local Plus controller performs burst read from LargeFlash or MostGraphic =
    memory only if an XLB master (CPU) or SCLPC interface initiates burst =
    access.
    
    In the case of CPU, you should enable cache for Local Plus memory.
    In the case of SCLPC, you should define BPT=3D8 in the SCLPC Control =
    Register (MBAR + 0x3C08).
    
    Other configurations doesn't force bursting.
    
    Thank you for your interest in Freescale Semiconductor products and for =
    the opportunity to serve you.
    Should you need to contact us with regard to this message, please see =
    the notes below.
    
    I hope its of some use.
    
    -WITTROCK
    
    
    
    --
    View this message in context: =
    http://www.nabble.com/LPC-burst-accesses-tp14270986p14274105.html
    Sent from the linuxppc-embedded mailing list archive at Nabble.com.
    
    _______________________________________________
    Linuxppc-embedded mailing list
    Linuxppc-embedded@ozlabs•org
    https://ozlabs.org/mailman/listinfo/linuxppc-embedded
    
    ^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2007-12-12 10:36 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2007-12-11  9:46 LPC burst accesses Kári Davíðsson
2007-12-11 13:43 ` WITTROCK
2007-12-12 10:36   ` Kári Davíðsson

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