* RE: Linuxppc-embedded Digest, Vol 26, Issue 36
[not found] <mailman.354.1161187327.32299.linuxppc-embedded@ozlabs.org>
@ 2006-10-19 1:10 ` Wang Matthew-R59995
2006-10-19 1:54 ` Kumar Gala
0 siblings, 1 reply; 2+ messages in thread
From: Wang Matthew-R59995 @ 2006-10-19 1:10 UTC (permalink / raw)
To: galak; +Cc: linuxppc-embedded
Hi Kumar,
Actually I do many trials about it. Vxwerks Bootrom is smaller than
U-Boot. The key difference between Bootrom and U-boot is that some
source code of Bootrom is invisible to the users.
Actually the rfi instruction which I point out is the first rfi
instruction of Linux PowerPC bringup.
Before that, it's TLB entry invalidation and temp TLB entry mapping.
I check MMU setting carefully before coming Linux Kernel.
I just want to know if other guys met similar scenario like me. I don't
need the precise answer, just overall suggestion about it because I
understand that not everyone has the same bootloader of mine, that
bootloader is actually a customized bootloader.
Anyway thank you.
R9 point to LR register, mask the high 20 bit of r9 and send to r7, and
then add 24, which means stride 6 instructions for rfi instruction
execution.
Of course, rfi can switch the TLB entry, both the previous TLB entry and
the temp TLB entry point to the same physical address.
I've checked it.
B.R
Wang Qi.
Date: Wed, 18 Oct 2006 08:39:23 -0500
From: Kumar Gala <galak@kernel•crashing.org>
Subject: Re: About the RFI instruction on Linux Powerpc
To: Wang Matthew-R59995 <Qi.W@freescale•com>
Cc: linuxppc-embedded@ozlabs•org
Message-ID: <0EE06CE5-98CB-49BB-A398-DF0E3277125D@kernel•crashing.org>
Content-Type: text/plain; charset=3DUS-ASCII; delsp=3Dyes; =
format=3Dflowed
On Oct 18, 2006, at 7:49 AM, Wang Matthew-R59995 wrote:
> Hi folks,
>
> Currently I meet an issue about rfi instruction. Please see the =20
> following source code. This source code is contained at the =20
> head_fsl_booke.h of ./arch/powerpc/kernel directory.
>
> xori r6,r4,1
> slwi r6,r6,5 /* setup new context with other address space */
> bl 1f /* Find our address */
> 1: mflr r9
> rlwimi r7,r9,0,20,31
> addi r7,r7,24
> mtspr SPRN_SRR0,r7
> mtspr SPRN_SRR1,r6
> rfi
> I found that rfi instruction can't jump to the address of SRR0. I =20
> take the MPC8555CDS board to do those test. And I don't take U-Boot =20
> as bootloader, while the Vxwerks Bootrom.
>
> I just want to try if Bootrom can bring up the Linux Powerpc kernel.
>
> Any suggestion for that?
What does happen after the rfi instruction? Do you have a JTAG =20
debugger or something you can use to single step through this code? =20
Do you know the value of r9?
There are some expectations as to what's setup by the bootloader when =20
you jump into the kernel. They are pretty minimal but I dont know if =20
the VxWorks Bootrom does the same thing as u-boot.
- kumar
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: Linuxppc-embedded Digest, Vol 26, Issue 36
2006-10-19 1:10 ` Linuxppc-embedded Digest, Vol 26, Issue 36 Wang Matthew-R59995
@ 2006-10-19 1:54 ` Kumar Gala
0 siblings, 0 replies; 2+ messages in thread
From: Kumar Gala @ 2006-10-19 1:54 UTC (permalink / raw)
To: Wang Matthew-R59995; +Cc: linuxppc-embedded
On Oct 18, 2006, at 8:10 PM, Wang Matthew-R59995 wrote:
> Hi Kumar,
>
> Actually I do many trials about it. Vxwerks Bootrom is smaller than
> U-Boot. The key difference between Bootrom and U-boot is that some
> source code of Bootrom is invisible to the users.
>
> Actually the rfi instruction which I point out is the first rfi
> instruction of Linux PowerPC bringup.
>
> Before that, it's TLB entry invalidation and temp TLB entry mapping.
>
> I check MMU setting carefully before coming Linux Kernel.
>
> I just want to know if other guys met similar scenario like me. I
> don't
> need the precise answer, just overall suggestion about it because I
> understand that not everyone has the same bootloader of mine, that
> bootloader is actually a customized bootloader.
I understand that, thus I was asking what exact problem you were
seeing to try and help.
> Anyway thank you.
>
> R9 point to LR register, mask the high 20 bit of r9 and send to r7,
> and
> then add 24, which means stride 6 instructions for rfi instruction
> execution.
>
> Of course, rfi can switch the TLB entry, both the previous TLB
> entry and
> the temp TLB entry point to the same physical address.
>
> I've checked it.
I know what the code does, I wrote it :)
- kumar
^ permalink raw reply [flat|nested] 2+ messages in thread
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2006-10-19 1:10 ` Linuxppc-embedded Digest, Vol 26, Issue 36 Wang Matthew-R59995
2006-10-19 1:54 ` Kumar Gala
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