* PCI BAR mapping problem
@ 2007-08-13 14:11 Johan Borkhuis
0 siblings, 0 replies; 2+ messages in thread
From: Johan Borkhuis @ 2007-08-13 14:11 UTC (permalink / raw)
To: linuxppc-embedded
Hello,
I am having some problems with the initialization of BAR registers of
the PCI bus. I have a number of devices connected to the bus, which have
a BAR-size of less than PAGE_SIZE. For example:
01:00.0 Network controller: VMIC: Unknown device 5565 (rev 01)
Subsystem: PLX Technology, Inc.: Unknown device 9656
Flags: bus master, 66Mhz, medium devsel, latency 128, IRQ 52
Memory at 00000000dfeffe00 (32-bit, non-prefetchable) [size=512]
I/O ports at e0ffff00 [size=256]
Memory at 00000000dfeffdc0 (32-bit, non-prefetchable) [size=64]
Memory at 00000000d8000000 (32-bit, non-prefetchable) [size=64M]
Capabilities: [40] Power Management version 0
Capabilities: [48] #00 [0080]
I want to access the PCI-areas from from user space, so I try to do an
mmap. The returned address is however rounded to multiple of PAGE_SIZE
(=0x1000). To access for example BAR0, I have to use the return-value
from mmap+0xE00. And in the above case, I am able to access the BAR0 and
BAR2 areas with only 1 mmap cal, as the 2 addresses are within one page.
The problem is that, when running my code on a I386 platform the BAR
registers are mapped at address 0x0 of the returned area.
When looking at the PCI init code (arch/ppc/syslib/pci_auto.c) I see
that the BAR-base address and/or size is not corrected for PAGE_SIZE. Is
this correct behaviour?
I could image the following line being changed from:
bar_value = (*upper_limit - bar_size) & ~(bar_size - 1);
to:
bar_value = ((*upper_limit - bar_size) & ~(bar_size - 1)) &
~(PAGE_SIZE-1);
The PCI area is assigned using a top-down method. Using this statement
the bar_value is rounded down to the first PAGE_SIZE boundary.
This gives the following output:
01:00.0 Network controller: VMIC: Unknown device 5565 (rev 01)
Subsystem: PLX Technology, Inc.: Unknown device 9656
Flags: bus master, 66Mhz, medium devsel, latency 128, IRQ 52
Memory at 00000000dfeff000 (32-bit, non-prefetchable) [size=512]
I/O ports at e0fff000 [size=256]
Memory at 00000000dfefe000 (32-bit, non-prefetchable) [size=64]
Memory at 00000000d8000000 (32-bit, non-prefetchable) [size=64M]
Capabilities: [40] Power Management version 0
Capabilities: [48] #00 [0080]
Kind regards,
Johan Borkhuis
^ permalink raw reply [flat|nested] 2+ messages in thread* PCI BAR mapping problem
@ 2007-08-13 20:23 Johan Borkhuis
0 siblings, 0 replies; 2+ messages in thread
From: Johan Borkhuis @ 2007-08-13 20:23 UTC (permalink / raw)
To: linuxppc-dev
Hello,
I am having some problems with the initialization of BAR registers of
the PCI bus. I have a number of devices connected to the bus, which have
a BAR-size of less than PAGE_SIZE. For example:
01:00.0 Network controller: VMIC: Unknown device 5565 (rev 01)
Subsystem: PLX Technology, Inc.: Unknown device 9656
Flags: bus master, 66Mhz, medium devsel, latency 128, IRQ 52
Memory at 00000000dfeffe00 (32-bit, non-prefetchable) [size=512]
I/O ports at e0ffff00 [size=256]
Memory at 00000000dfeffdc0 (32-bit, non-prefetchable) [size=64]
Memory at 00000000d8000000 (32-bit, non-prefetchable) [size=64M]
Capabilities: [40] Power Management version 0
Capabilities: [48] #00 [0080]
I want to access the PCI-areas from from user space, so I try to do an
mmap. The returned address is however rounded to multiple of PAGE_SIZE
(=0x1000). To access for example BAR0, I have to use the return-value
from mmap+0xE00. And in the above case, I am able to access the BAR0 and
BAR2 areas with only 1 mmap call, as the 2 addresses are within one page.
The problem is that, when running my code on a I386 platform the BAR
registers are mapped at address 0x0 of the returned area.
When looking at the PCI init code (arch/ppc/syslib/pci_auto.c) I see
that the BAR-base address and/or size is not corrected for PAGE_SIZE. Is
this correct behaviour?
I could image the following line being changed from:
bar_value = (*upper_limit - bar_size) & ~(bar_size - 1);
to:
bar_value = ((*upper_limit - bar_size) & ~(bar_size - 1)) &
~(PAGE_SIZE-1);
The PCI area is assigned using a top-down method. Using this statement
the bar_value is rounded down to the first PAGE_SIZE boundary.
This gives the following output:
01:00.0 Network controller: VMIC: Unknown device 5565 (rev 01)
Subsystem: PLX Technology, Inc.: Unknown device 9656
Flags: bus master, 66Mhz, medium devsel, latency 128, IRQ 52
Memory at 00000000dfeff000 (32-bit, non-prefetchable) [size=512]
I/O ports at e0fff000 [size=256]
Memory at 00000000dfefe000 (32-bit, non-prefetchable) [size=64]
Memory at 00000000d8000000 (32-bit, non-prefetchable) [size=64M]
Capabilities: [40] Power Management version 0
Capabilities: [48] #00 [0080]
My architecture: MVME3100 board with PPC8540 processor.
Note:
I posted this message to the embedded PPC mailing list, but as this is a
more generic linux-ppc issue, it could be discussed here as well.
Kind regards,
Johan Borkhuis
--
o o o o o o o . . . ___J_o_h_a_n___B_o_r_k_h_u_i_s___
o _____ || http://www.borkhuis.com |
.][__n_n_|DD[ ====_____ | johan@borkhuis•com |
>(________|__|_[_________]_|______________________________|
_/oo OOOOO oo` ooo ooo 'o!o!o o!o!o`
=== VxWorks-FAQ: http://www.xs4all.nl/~borkhuis/vxworks/vxworks.html ===
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2007-08-13 20:31 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-08-13 14:11 PCI BAR mapping problem Johan Borkhuis
-- strict thread matches above, loose matches on Subject: below --
2007-08-13 20:23 Johan Borkhuis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox