From: Sergei Shtylyov <sshtylyov@ru•mvista.com>
To: Stephen Neuendorffer <stephen.neuendorffer@xilinx•com>
Cc: John Linn <linnj@xilinx•com>, linuxppc-dev@ozlabs•org
Subject: Re: [PATCH 2/3][POWERPC][V2] Xilinx: of_serial support for Xilinx uart 16550.
Date: Thu, 03 Apr 2008 15:59:32 +0400 [thread overview]
Message-ID: <47F4C6A4.2020307@ru.mvista.com> (raw)
In-Reply-To: <20080402213919.C261F5E007F@mail91-dub.bigfish.com>
Hello.
Stephen Neuendorffer wrote:
> I don't think big-endian has the same context as reg-shift/reg-offset.
The "big-endian" is about how the byte addresses are laid out, so the
context is the same -- in this case, it would determine where each UART
register is located within the address stride specified by "reg-shift".
It'll alwaay be at offset 0 or (2 << reg-shift) - 1 (unless some vendor goes
and implements something with "middle-endian" layout of course :-)
> The OpenPOC is fundamentally a 32 bit device, but ns16550 is not... If
So what?
> we were talking about a 32 bit device, then I'd probably agree with you,
There are 16550 clones that *are* 32-bit.
> but in this case, the reg-shift
I'm not arguing about "reg-shift" already -- look like it's been spec'ed. :-)
> (and to some extent) reg-offset have
> been used before and probably make more sense, I think.
The "reg-offset" has been used before? Where?
> Steve
WBR, Sergei
next prev parent reply other threads:[~2008-04-03 12:00 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <689CB232690D8D4E97DA6C76DA098E6C05FC4762@XCO-EXCHVS1.xlnx.xilinx.com>
2008-04-02 21:39 ` [PATCH 2/3][POWERPC][V2] Xilinx: of_serial support for Xilinx uart 16550 Stephen Neuendorffer
2008-04-03 11:59 ` Sergei Shtylyov [this message]
[not found] <12071551351007-git-send-email-john.linn@xilinx.com>
[not found] ` <12071551354058-git-send-email-john.linn@xilinx.com>
2008-04-02 16:52 ` John Linn
2008-04-02 18:00 ` Grant Likely
2008-04-02 18:20 ` John Linn
2008-04-02 19:27 ` Grant Likely
2008-04-02 19:19 ` Sergei Shtylyov
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