* AW: How to set DDR data bus width to 16Bit
@ 2009-07-02 9:45 Frank Prepelica
2009-07-02 10:30 ` Norbert van Bolhuis
0 siblings, 1 reply; 2+ messages in thread
From: Frank Prepelica @ 2009-07-02 9:45 UTC (permalink / raw)
To: Norbert van Bolhuis; +Cc: linuxppc-dev
> you have to do it via your bootloader (u-boot) which sets up
> the DDR memory controller.
> Linux (already) assumes memory is available.
> Are you sure linux kernel is changing DDR_SDRAM_CFG ?
> When our linux-2.6.28 kernel is up, it's still 0xc3080000 when I read
> physical address 0xe0002110.
Hi Norbert, thank you for your fast reply!
You are absolutly right! I made a silly mistake. I've read the value of
the 0xe0002110 with a 8bit pointer.
The value is actually 0xC3100000 which means the 16bit bus width is set.
Just to be sure. Is this the only change (in the bootloader) I have to
make that all data accesses are 16bit wide?
> Btw. We did some performance tests with 16 bit bus-width (DDR2 memory)
> and surprisingly performance was almost as good as 32 bit bus-width
This is exactly our intention to test. Thanks for that hint. Very good
to
know!
Thank you.
Best regards
Frank
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: AW: How to set DDR data bus width to 16Bit
2009-07-02 9:45 AW: How to set DDR data bus width to 16Bit Frank Prepelica
@ 2009-07-02 10:30 ` Norbert van Bolhuis
0 siblings, 0 replies; 2+ messages in thread
From: Norbert van Bolhuis @ 2009-07-02 10:30 UTC (permalink / raw)
To: Frank Prepelica; +Cc: linuxppc-dev
Hi Frank,
Yes, it's 0xC3100000 for 16 bit. I showed the 32bit value.
Yes, to go to 16 bit bus-width (1 DDR(2) device), this is the only
change needed in u-boot, assuming you have 2 DDR(2) devices (like 8313E-RDB)
which together provide 16+16 = 32bit bus-width.
Since, surprisingly, the 16 bit application/u-boot performance was almost as
good as 32 bit we even tested with I-cache and D-cache turned off.
u-boot provides commands for this (which I didn't know, see some previous
emails from me on this mailing-list).
Also with I-cache and D-cache turned off the 16 bit bus-width performance was
almost as good as 32 bit. So our conclusion was that the 16/32 bit DDR2 memory
access is not the limiting factor when it comes to "SW performance".
Therefore we decided to go for 16 bit bus-width for a new/tiny 8313 based
design.
Please let me know your test results. I would expect you to conclude more
or less the same.
Best Regards,
Norbert.
Frank Prepelica wrote:
>> you have to do it via your bootloader (u-boot) which sets up
>> the DDR memory controller.
>> Linux (already) assumes memory is available.
>> Are you sure linux kernel is changing DDR_SDRAM_CFG ?
>> When our linux-2.6.28 kernel is up, it's still 0xc3080000 when I read
>> physical address 0xe0002110.
>
>
> Hi Norbert, thank you for your fast reply!
>
> You are absolutly right! I made a silly mistake. I've read the value of
> the 0xe0002110 with a 8bit pointer.
>
> The value is actually 0xC3100000 which means the 16bit bus width is set.
>
> Just to be sure. Is this the only change (in the bootloader) I have to
> make that all data accesses are 16bit wide?
>
>> Btw. We did some performance tests with 16 bit bus-width (DDR2 memory)
>> and surprisingly performance was almost as good as 32 bit bus-width
>
> This is exactly our intention to test. Thanks for that hint. Very good
> to
> know!
>
> Thank you.
>
> Best regards
> Frank
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2009-07-02 10:31 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-07-02 9:45 AW: How to set DDR data bus width to 16Bit Frank Prepelica
2009-07-02 10:30 ` Norbert van Bolhuis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox