From: "Michael Chan" <mchan@broadcom•com>
To: "Anton Blanchard" <anton@samba•org>
Cc: "Matthew Carlson" <mcarlson@broadcom•com>,
"davem@davemloft•net" <davem@davemloft•net>,
"netdev@vger•kernel.org" <netdev@vger•kernel.org>,
"andy@greyhouse•net" <andy@greyhouse•net>
Subject: Re: [PATCH net-next 09/14] tg3: Improve small packet performance
Date: Wed, 4 Aug 2010 15:47:29 -0700 [thread overview]
Message-ID: <1280962049.7554.25.camel@HP1> (raw)
In-Reply-To: <20100804222741.GA18708@kryten>
On Wed, 2010-08-04 at 15:27 -0700, Anton Blanchard wrote:
> Hi,
>
> Just saw this go in:
>
> > static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
> > {
> > - smp_mb();
> > + /* Tell compiler to fetch tx indices from memory. */
> > + barrier();
> > return tnapi->tx_pending -
> > ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
> > }
>
> Which worries me. Are we sure we don't need any ordering (eg smp_rmb)?
> A compiler barrier does nothing to ensure two loads are ordered.
We generally only get an estimate of the available tx ring size when we
call tg3_tx_avail(), so memory barriers are not generally needed. We
put a compiler barrier there to make sure that the compiler will fetch
the tx_prod and tx_cons from memory to give us a better estimate.
In specific cases detailed in the patch description, we do need memory
barriers when we call netif_tx_stop_queue() and then check for the tx
ring. We decided to put memory barriers exactly where they're needed
instead of inside tg3_tx_avail() which is an overkill.
Thanks.
next prev parent reply other threads:[~2010-08-04 22:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-02 21:26 [PATCH net-next 09/14] tg3: Improve small packet performance Matt Carlson
2010-08-04 22:27 ` Anton Blanchard
2010-08-04 22:46 ` Matt Carlson
2010-08-04 22:47 ` Michael Chan [this message]
2010-08-04 23:08 ` Anton Blanchard
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