From: Rob Herring <robh@kernel•org>
To: Srinivas Goud <srinivas.goud@amd•com>
Cc: wg@grandegger•com, mkl@pengutronix•de, davem@davemloft•net,
edumazet@google•com, kuba@kernel•org, pabeni@redhat•com,
krzysztof.kozlowski+dt@linaro•org, conor+dt@kernel•org,
p.zabel@pengutronix•de, git@amd•com, michal.simek@amd•com,
linux-can@vger•kernel.org, linux-arm-kernel@lists•infradead.org,
linux-kernel@vger•kernel.org, netdev@vger•kernel.org,
devicetree@vger•kernel.org, appana.durga.rao@xilinx•com,
naga.sureshkumar.relli@xilinx•com
Subject: Re: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc'
Date: Mon, 28 Aug 2023 10:43:09 -0500 [thread overview]
Message-ID: <20230828154309.GA604444-robh@kernel.org> (raw)
In-Reply-To: <1693234725-3615719-2-git-send-email-srinivas.goud@amd.com>
On Mon, Aug 28, 2023 at 08:28:43PM +0530, Srinivas Goud wrote:
> ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller.
> Part of this feature configuration and counter registers added in
> IP for 1bit/2bit ECC errors.
>
> xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller
> node if ECC block enabled in the HW
>
> Signed-off-by: Srinivas Goud <srinivas.goud@amd•com>
> ---
> Changes in v3:
> Update commit description
>
> Changes in v2:
> None
Doesn't apply, dependency?
>
> Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> index 64d57c3..c842610 100644
> --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> @@ -49,6 +49,10 @@ properties:
> resets:
> maxItems: 1
>
> + xlnx,has-ecc:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: CAN Tx and Rx fifo ECC enable flag (AXI CAN)
has ECC or enable ECC?
> +
> required:
> - compatible
> - reg
> @@ -137,6 +141,7 @@ examples:
> interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
> tx-fifo-depth = <0x40>;
> rx-fifo-depth = <0x40>;
> + xlnx,has-ecc
Obviously not tested.
> };
>
> - |
> --
> 2.1.1
>
next prev parent reply other threads:[~2023-08-28 15:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-28 14:58 [PATCH v3 0/3] can: xilinx_can: Add ECC feature support Srinivas Goud
2023-08-28 14:58 ` [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc' Srinivas Goud
2023-08-28 15:43 ` Rob Herring [this message]
2023-08-30 6:06 ` Goud, Srinivas
2023-08-30 7:13 ` Krzysztof Kozlowski
2023-08-30 7:45 ` Goud, Srinivas
2023-08-28 14:58 ` [PATCH v3 2/3] can: xilinx_can: Add ECC support Srinivas Goud
2023-08-28 14:58 ` [PATCH v3 3/3] can: xilinx_can: Add ethtool stats interface for ECC errors Srinivas Goud
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