From: Saeed Mahameed <saeed@kernel•org>
To: "David S. Miller" <davem@davemloft•net>,
Jakub Kicinski <kuba@kernel•org>, Paolo Abeni <pabeni@redhat•com>,
Eric Dumazet <edumazet@google•com>
Cc: Saeed Mahameed <saeedm@nvidia•com>,
netdev@vger•kernel.org, Tariq Toukan <tariqt@nvidia•com>,
Gal Pressman <gal@nvidia•com>,
Leon Romanovsky <leonro@nvidia•com>,
Carolina Jubran <cjubran@nvidia•com>,
Cosmin Ratiu <cratiu@nvidia•com>
Subject: [net 4/7] net/mlx5: Explicitly set scheduling element and TSAR type
Date: Mon, 9 Sep 2024 12:45:02 -0700 [thread overview]
Message-ID: <20240909194505.69715-5-saeed@kernel.org> (raw)
In-Reply-To: <20240909194505.69715-1-saeed@kernel.org>
From: Carolina Jubran <cjubran@nvidia•com>
Ensure the scheduling element type and TSAR type are explicitly
initialized in the QoS rate group creation.
This prevents potential issues due to default values.
Fixes: 1ae258f8b343 ("net/mlx5: E-switch, Introduce rate limiting groups API")
Signed-off-by: Carolina Jubran <cjubran@nvidia•com>
Reviewed-by: Cosmin Ratiu <cratiu@nvidia•com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia•com>
---
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
index 20146a2dc7f4..997c412a81af 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
@@ -421,6 +421,7 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex
{
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
struct mlx5_esw_rate_group *group;
+ __be32 *attr;
u32 divider;
int err;
@@ -428,6 +429,12 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex
if (!group)
return ERR_PTR(-ENOMEM);
+ MLX5_SET(scheduling_context, tsar_ctx, element_type,
+ SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);
+
+ attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);
+ *attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);
+
MLX5_SET(scheduling_context, tsar_ctx, parent_element_id,
esw->qos.root_tsar_ix);
err = mlx5_create_scheduling_element_cmd(esw->dev,
--
2.46.0
next prev parent reply other threads:[~2024-09-09 19:45 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-09 19:44 [pull request][net 0/7] mlx5 fixes 2024-09-09 Saeed Mahameed
2024-09-09 19:44 ` [net 1/7] net/mlx5: Update the list of the PCI supported devices Saeed Mahameed
2024-09-11 3:20 ` patchwork-bot+netdevbpf
2024-09-09 19:45 ` [net 2/7] net/mlx5e: Add missing link modes to ptys2ethtool_map Saeed Mahameed
2024-09-09 19:45 ` [net 3/7] net/mlx5e: Add missing link mode to ptys2ext_ethtool_map Saeed Mahameed
2024-09-09 19:45 ` Saeed Mahameed [this message]
2024-09-09 19:45 ` [net 5/7] net/mlx5: Add missing masks and QoS bit masks for scheduling elements Saeed Mahameed
2024-09-09 19:45 ` [net 6/7] net/mlx5: Verify support for scheduling element and TSAR type Saeed Mahameed
2024-09-09 19:45 ` [net 7/7] net/mlx5: Fix bridge mode operations when there are no VFs Saeed Mahameed
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