From: Jakub Kicinski <kuba@kernel•org>
To: "Nitka, Grzegorz" <grzegorz.nitka@intel•com>
Cc: "netdev@vger•kernel.org" <netdev@vger•kernel.org>,
"linux-kernel@vger•kernel.org" <linux-kernel@vger•kernel.org>,
"intel-wired-lan@lists•osuosl.org"
<intel-wired-lan@lists•osuosl.org>,
"Oros, Petr" <poros@redhat•com>,
"richardcochran@gmail•com" <richardcochran@gmail•com>,
"andrew+netdev@lunn•ch" <andrew+netdev@lunn•ch>,
"Kitszel, Przemyslaw" <przemyslaw.kitszel@intel•com>,
"Nguyen, Anthony L" <anthony.l.nguyen@intel•com>,
"Prathosh.Satish@microchip•com" <Prathosh.Satish@microchip•com>,
"Vecera, Ivan" <ivecera@redhat•com>,
"jiri@resnulli•us" <jiri@resnulli•us>,
"Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel•com>,
"vadim.fedorenko@linux•dev" <vadim.fedorenko@linux•dev>,
"donald.hunter@gmail•com" <donald.hunter@gmail•com>,
"horms@kernel•org" <horms@kernel•org>,
"pabeni@redhat•com" <pabeni@redhat•com>,
"davem@davemloft•net" <davem@davemloft•net>,
"edumazet@google•com" <edumazet@google•com>
Subject: Re: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825
Date: Fri, 5 Jun 2026 16:26:15 -0700 [thread overview]
Message-ID: <20260605162615.0987ff2a@kernel.org> (raw)
In-Reply-To: <IA1PR11MB6219C1EF3BF8160226E5826992112@IA1PR11MB6219.namprd11.prod.outlook.com>
On Fri, 5 Jun 2026 16:10:19 +0000 Nitka, Grzegorz wrote:
> Hi Kuba. Just submitted v13.
>
> It includes the following fixes for pre-existing issues:
> - dpll core fixes. Each AI review concern (3) is addressed in separate
> commit. If you think it's better to squash them, let me know (however
> it addresses issues from two different 'old' commits).
> Also, the hint form AI to use different dpll xa_array (parent not pin) to
> address one of the issues, it simply does not work (WARNING flood observed,
> more details in patch 3/11)
> - ice driver fix for potential hung on flush_workqueue in error path for FW node pins
>
> As you noted, two other pre-existing issues are covered by ICE_FLAG_DPLL.
> I left the code as it is for those concerns.
> There is one more pre-existing one, related to ice_ptp_link_change. As the fix seems to be
> rather simple one, I believe I need more time for more comprehensive testing.
> So my preference is to go with standard fix-path on 'net'.
SG, thanks!
BTW either you or Arkadiusz should chime in on the NCO thread, please:
https://lore.kernel.org/all/20260531194423.383366-2-ivecera@redhat.com/
Shouldn't take much time to express an opinion, I hope.
prev parent reply other threads:[~2026-06-05 23:26 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 14:26 [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 1/8] dpll: add generic DPLL type Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 3/8] dpll: extend pin notifier with notification source ID Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 4/8] dpll: allow fwnode pins to attempt state change without capability bit Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
2026-06-04 1:30 ` [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Jakub Kicinski
2026-06-04 20:05 ` Nitka, Grzegorz
2026-06-04 22:54 ` Jakub Kicinski
2026-06-05 16:10 ` Nitka, Grzegorz
2026-06-05 23:26 ` Jakub Kicinski [this message]
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