* [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
@ 2025-12-18 9:44 Grzegorz Nitka
2026-01-05 16:34 ` Simon Horman
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Grzegorz Nitka @ 2025-12-18 9:44 UTC (permalink / raw)
To: intel-wired-lan
Cc: netdev, anthony.l.nguyen, przemyslaw.kitszel, Grzegorz Nitka,
Aleksandr Loktionov
Fix incorrect 'adjust the timer' programming sequence for E830 devices
series. Only shadow registers GLTSYN_SHADJ were programmed in the
current implementation. According to the specification [1], write to
command GLTSYN_CMD register is also required with CMD field set to
"Adjust the Time" value, for the timer adjustment to take the effect.
The flow was broken for the adjustment less than S32_MAX/MIN range
(around +/- 2 seconds). For bigger adjustment, non-atomic programming
flow is used, involving set timer programming. Non-atomic flow is
implemented correctly.
Testing hints:
Run command:
phc_ctl /dev/ptpX get adj 2 get
Expected result:
Returned timstamps differ at least by 2 seconds
[1] Intel® Ethernet Controller E830 Datasheet rev 1.3, chapter 9.7.5.4
https://cdrdv2.intel.com/v1/dl/getContent/787353?explicitVersion=true
Fixes: f00307522786 ("ice: Implement PTP support for E830 devices")
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel•com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel•com>
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 35680dbe4a7f..161a0ae8599c 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -5381,8 +5381,8 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
*/
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
{
+ int err = 0;
u8 tmr_idx;
- int err;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@@ -5399,8 +5399,8 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
err = ice_ptp_prep_phy_adj_e810(hw, adj);
break;
case ICE_MAC_E830:
- /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */
- return 0;
+ /* E830 sync PHYs automatically after setting cmd register */
+ break;
case ICE_MAC_GENERIC:
err = ice_ptp_prep_phy_adj_e82x(hw, adj);
break;
base-commit: 8282ed7f73cf08f99288d3d0131e07f149063fbe
--
2.39.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
2025-12-18 9:44 [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices Grzegorz Nitka
@ 2026-01-05 16:34 ` Simon Horman
2026-01-07 10:09 ` Loktionov, Aleksandr
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Simon Horman @ 2026-01-05 16:34 UTC (permalink / raw)
To: Grzegorz Nitka
Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel,
Aleksandr Loktionov
On Thu, Dec 18, 2025 at 10:44:28AM +0100, Grzegorz Nitka wrote:
> Fix incorrect 'adjust the timer' programming sequence for E830 devices
> series. Only shadow registers GLTSYN_SHADJ were programmed in the
> current implementation. According to the specification [1], write to
> command GLTSYN_CMD register is also required with CMD field set to
> "Adjust the Time" value, for the timer adjustment to take the effect.
>
> The flow was broken for the adjustment less than S32_MAX/MIN range
> (around +/- 2 seconds). For bigger adjustment, non-atomic programming
> flow is used, involving set timer programming. Non-atomic flow is
> implemented correctly.
>
> Testing hints:
> Run command:
> phc_ctl /dev/ptpX get adj 2 get
> Expected result:
> Returned timstamps differ at least by 2 seconds
>
> [1] Intel® Ethernet Controller E830 Datasheet rev 1.3, chapter 9.7.5.4
> https://cdrdv2.intel.com/v1/dl/getContent/787353?explicitVersion=true
>
> Fixes: f00307522786 ("ice: Implement PTP support for E830 devices")
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel•com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel•com>
Reviewed-by: Simon Horman <horms@kernel•org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
2025-12-18 9:44 [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices Grzegorz Nitka
2026-01-05 16:34 ` Simon Horman
@ 2026-01-07 10:09 ` Loktionov, Aleksandr
2026-03-25 3:09 ` [Intel-wired-lan] " Rinitha, SX
2026-03-25 23:43 ` Jacob Keller
3 siblings, 0 replies; 5+ messages in thread
From: Loktionov, Aleksandr @ 2026-01-07 10:09 UTC (permalink / raw)
To: Nitka, Grzegorz, intel-wired-lan@lists•osuosl.org
Cc: netdev@vger•kernel.org, Nguyen, Anthony L, Kitszel, Przemyslaw
> -----Original Message-----
> From: Nitka, Grzegorz <grzegorz.nitka@intel•com>
> Sent: Thursday, December 18, 2025 10:44 AM
> To: intel-wired-lan@lists•osuosl.org
> Cc: netdev@vger•kernel.org; Nguyen, Anthony L
> <anthony.l.nguyen@intel•com>; Kitszel, Przemyslaw
> <przemyslaw.kitszel@intel•com>; Nitka, Grzegorz
> <grzegorz.nitka@intel•com>; Loktionov, Aleksandr
> <aleksandr.loktionov@intel•com>
> Subject: [PATCH iwl-net] ice: fix 'adjust' timer programming for E830
> devices
>
> Fix incorrect 'adjust the timer' programming sequence for E830 devices
> series. Only shadow registers GLTSYN_SHADJ were programmed in the
> current implementation. According to the specification [1], write to
> command GLTSYN_CMD register is also required with CMD field set to
> "Adjust the Time" value, for the timer adjustment to take the effect.
>
> The flow was broken for the adjustment less than S32_MAX/MIN range
> (around +/- 2 seconds). For bigger adjustment, non-atomic programming
> flow is used, involving set timer programming. Non-atomic flow is
> implemented correctly.
>
> Testing hints:
> Run command:
> phc_ctl /dev/ptpX get adj 2 get
> Expected result:
> Returned timstamps differ at least by 2 seconds
>
> [1] Intel® Ethernet Controller E830 Datasheet rev 1.3, chapter 9.7.5.4
> https://cdrdv2.intel.com/v1/dl/getContent/787353?explicitVersion=true
>
> Fixes: f00307522786 ("ice: Implement PTP support for E830 devices")
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel•com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel•com>
> ---
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> index 35680dbe4a7f..161a0ae8599c 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> @@ -5381,8 +5381,8 @@ int ice_ptp_write_incval_locked(struct ice_hw
> *hw, u64 incval)
> */
> int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) {
> + int err = 0;
> u8 tmr_idx;
> - int err;
>
> tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
>
> @@ -5399,8 +5399,8 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32
> adj)
> err = ice_ptp_prep_phy_adj_e810(hw, adj);
> break;
> case ICE_MAC_E830:
> - /* E830 sync PHYs automatically after setting
> GLTSYN_SHADJ */
> - return 0;
> + /* E830 sync PHYs automatically after setting cmd
> register */
> + break;
> case ICE_MAC_GENERIC:
> err = ice_ptp_prep_phy_adj_e82x(hw, adj);
> break;
>
> base-commit: 8282ed7f73cf08f99288d3d0131e07f149063fbe
> --
> 2.39.3
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel•com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [Intel-wired-lan] [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
2025-12-18 9:44 [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices Grzegorz Nitka
2026-01-05 16:34 ` Simon Horman
2026-01-07 10:09 ` Loktionov, Aleksandr
@ 2026-03-25 3:09 ` Rinitha, SX
2026-03-25 23:43 ` Jacob Keller
3 siblings, 0 replies; 5+ messages in thread
From: Rinitha, SX @ 2026-03-25 3:09 UTC (permalink / raw)
To: Nitka, Grzegorz, intel-wired-lan@lists•osuosl.org
Cc: Loktionov, Aleksandr, netdev@vger•kernel.org, Nguyen, Anthony L,
Kitszel, Przemyslaw
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl•org> On Behalf Of Grzegorz Nitka
> Sent: 18 December 2025 15:14
> To: intel-wired-lan@lists•osuosl.org
> Cc: Loktionov, Aleksandr <aleksandr.loktionov@intel•com>; netdev@vger•kernel.org; Nguyen, Anthony L <anthony.l.nguyen@intel•com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel•com>
> Subject: [Intel-wired-lan] [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
>
> Fix incorrect 'adjust the timer' programming sequence for E830 devices series. Only shadow registers GLTSYN_SHADJ were programmed in the current implementation. According to the specification [1], write to command GLTSYN_CMD register is also required with CMD field set to "Adjust the Time" value, for the timer adjustment to take the effect.
>
> The flow was broken for the adjustment less than S32_MAX/MIN range (around +/- 2 seconds). For bigger adjustment, non-atomic programming flow is used, involving set timer programming. Non-atomic flow is implemented correctly.
>
> Testing hints:
> Run command:
> phc_ctl /dev/ptpX get adj 2 get
> Expected result:
> Returned timstamps differ at least by 2 seconds
>
> [1] Intel® Ethernet Controller E830 Datasheet rev 1.3, chapter 9.7.5.4 https://cdrdv2.intel.com/v1/dl/getContent/787353?explicitVersion=true
>
> Fixes: f00307522786 ("ice: Implement PTP support for E830 devices")
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel•com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel•com>
> ---
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel•com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
2025-12-18 9:44 [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices Grzegorz Nitka
` (2 preceding siblings ...)
2026-03-25 3:09 ` [Intel-wired-lan] " Rinitha, SX
@ 2026-03-25 23:43 ` Jacob Keller
3 siblings, 0 replies; 5+ messages in thread
From: Jacob Keller @ 2026-03-25 23:43 UTC (permalink / raw)
To: Grzegorz Nitka, intel-wired-lan
Cc: netdev, anthony.l.nguyen, przemyslaw.kitszel, Aleksandr Loktionov
On 12/18/2025 1:44 AM, Grzegorz Nitka wrote:
> Fix incorrect 'adjust the timer' programming sequence for E830 devices
> series. Only shadow registers GLTSYN_SHADJ were programmed in the
> current implementation. According to the specification [1], write to
> command GLTSYN_CMD register is also required with CMD field set to
> "Adjust the Time" value, for the timer adjustment to take the effect.
>
> The flow was broken for the adjustment less than S32_MAX/MIN range
> (around +/- 2 seconds). For bigger adjustment, non-atomic programming
> flow is used, involving set timer programming. Non-atomic flow is
> implemented correctly.
>
Ah, good catch!
Reviewed-by: Jacob Keller <jacob.e.keller@intel•com>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-12-18 9:44 [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices Grzegorz Nitka
2026-01-05 16:34 ` Simon Horman
2026-01-07 10:09 ` Loktionov, Aleksandr
2026-03-25 3:09 ` [Intel-wired-lan] " Rinitha, SX
2026-03-25 23:43 ` Jacob Keller
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