From: James Clark <james.clark@linaro•org>
To: Leo Yan <leo.yan@arm•com>
Cc: linux-arm-kernel@lists•infradead.org, coresight@lists•linaro.org,
linux-perf-users@vger•kernel.org, Leo Yan <leo.yan@linux•dev>,
Arnaldo Carvalho de Melo <acme@kernel•org>,
John Garry <john.g.garry@oracle•com>,
Will Deacon <will@kernel•org>, Mike Leach <mike.leach@arm•com>,
Suzuki K Poulose <suzuki.poulose@arm•com>,
Namhyung Kim <namhyung@kernel•org>,
Mark Rutland <mark.rutland@arm•com>,
Alexander Shishkin <alexander.shishkin@linux•intel.com>,
Jiri Olsa <jolsa@kernel•org>, Ian Rogers <irogers@google•com>,
Adrian Hunter <adrian.hunter@intel•com>,
Al Grant <al.grant@arm•com>,
Paschalis Mpeis <paschalis.mpeis@arm•com>,
Amir Ayupov <aaupov@fb•com>
Subject: Re: [PATCH v6 2/8] perf cs-etm: Refactor instruction size handling
Date: Thu, 4 Jun 2026 15:11:12 +0100 [thread overview]
Message-ID: <02fe627c-9a98-4de2-9bf4-6ce35bb470db@linaro.org> (raw)
In-Reply-To: <20260526-b4-arm_cs_callchain_support_v1-v6-2-f9f49f53c9dd@arm.com>
On 26/05/2026 5:59 pm, Leo Yan wrote:
> From: Leo Yan <leo.yan@linaro•org>
>
> This patch introduces a new function cs_etm__instr_size() to calculate
> the instruction size based on ISA type and instruction address.
>
> Given the trace data can be MB and most likely that will be A64/A32 on
> a lot of platforms, cs_etm__instr_addr() keeps a single ISA type check
> for A64/A32 and executes an optimized calculation (addr + offset * 4).
>
> Signed-off-by: Leo Yan <leo.yan@linaro•org>
> Signed-off-by: Leo Yan <leo.yan@arm•com>
> ---
> tools/perf/util/cs-etm.c | 44 +++++++++++++++++++++++---------------------
> 1 file changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
> index ab79d08f5a6095448470e2c3ec85ff3db2fb5634..5bff8811d61e423463b7bd4e20d599d5b5307a1a 100644
> --- a/tools/perf/util/cs-etm.c
> +++ b/tools/perf/util/cs-etm.c
> @@ -1347,6 +1347,17 @@ static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq,
> return ((instrBytes[1] & 0xF8) >= 0xE8) ? 4 : 2;
> }
>
> +static inline int cs_etm__instr_size(struct cs_etm_queue *etmq,
> + u8 trace_chan_id,
> + enum cs_etm_isa isa, u64 addr)
> +{
> + if (isa == CS_ETM_ISA_T32)
> + return cs_etm__t32_instr_size(etmq, trace_chan_id, addr);
> +
> + /* Otherwise, 4-byte instruction size for A32/A64 */
> + return 4;
> +}
> +
> static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet)
> {
> /*
> @@ -1375,19 +1386,18 @@ static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq,
> const struct cs_etm_packet *packet,
> u64 offset)
> {
> - if (packet->isa == CS_ETM_ISA_T32) {
> - u64 addr = packet->start_addr;
> + u64 addr = packet->start_addr;
>
> - while (offset) {
> - addr += cs_etm__t32_instr_size(etmq,
> - trace_chan_id, addr);
> - offset--;
> - }
> - return addr;
> - }
> + /* 4-byte instruction size for A32/A64 */
> + if (packet->isa == CS_ETM_ISA_A64 || packet->isa == CS_ETM_ISA_A32)
> + return addr + offset * 4;
>
> - /* Assume a 4 byte instruction size (A32/A64) */
> - return packet->start_addr + offset * 4;
> + while (offset) {
> + addr += cs_etm__instr_size(etmq, trace_chan_id,
> + packet->isa, addr);
> + offset--;
> + }
> + return addr;
> }
>
> static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq,
> @@ -1540,16 +1550,8 @@ static void cs_etm__copy_insn(struct cs_etm_queue *etmq,
> return;
> }
>
> - /*
> - * T32 instruction size might be 32-bit or 16-bit, decide by calling
> - * cs_etm__t32_instr_size().
> - */
> - if (packet->isa == CS_ETM_ISA_T32)
> - sample->insn_len = cs_etm__t32_instr_size(etmq, trace_chan_id,
> - sample->ip);
> - /* Otherwise, A64 and A32 instruction size are always 32-bit. */
> - else
> - sample->insn_len = 4;
> + sample->insn_len = cs_etm__instr_size(etmq, trace_chan_id,
> + packet->isa, sample->ip);
>
> cs_etm__mem_access(etmq, trace_chan_id, sample->ip, sample->insn_len,
> (void *)sample->insn, 0);
>
Reviewed-by: James Clark <james.clark@linaro•org>
next prev parent reply other threads:[~2026-06-04 14:11 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 16:59 [PATCH v6 0/8] perf cs-etm: Support thread stack and callchain Leo Yan
2026-05-26 16:59 ` [PATCH v6 1/8] perf cs-etm: Decode ETE exception packets Leo Yan
2026-06-04 14:10 ` James Clark
2026-05-26 16:59 ` [PATCH v6 2/8] perf cs-etm: Refactor instruction size handling Leo Yan
2026-06-04 14:11 ` James Clark [this message]
2026-05-26 16:59 ` [PATCH v6 3/8] perf cs-etm: Use thread-stack for last branch entries Leo Yan
2026-06-04 14:09 ` James Clark
2026-05-26 16:59 ` [PATCH v6 4/8] perf cs-etm: Flush thread stacks after decoder reset Leo Yan
2026-06-04 14:12 ` James Clark
2026-05-26 16:59 ` [PATCH v6 5/8] perf cs-etm: Support call indentation Leo Yan
2026-06-04 14:24 ` James Clark
2026-05-26 16:59 ` [PATCH v6 6/8] perf cs-etm: Filter synthesized branch samples Leo Yan
2026-06-04 14:42 ` James Clark
2026-05-26 16:59 ` [PATCH v6 7/8] perf cs-etm: Synthesize callchains for instruction samples Leo Yan
2026-06-04 15:07 ` James Clark
2026-05-26 16:59 ` [PATCH v6 8/8] perf test: Add Arm CoreSight callchain test Leo Yan
2026-05-29 14:57 ` [PATCH v6 0/8] perf cs-etm: Support thread stack and callchain Arnaldo Carvalho de Melo
2026-06-01 11:03 ` Leo Yan
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