From: Jerome Brunet <jbrunet@baylibre•com>
To: Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel•org>
Cc: Michael Turquette <mturquette@baylibre•com>,
Stephen Boyd <sboyd@kernel•org>, Rob Herring <robh@kernel•org>,
Krzysztof Kozlowski <krzk+dt@kernel•org>,
Conor Dooley <conor+dt@kernel•org>,
Neil Armstrong <neil.armstrong@linaro•org>,
Xianwei Zhao <xianwei.zhao@amlogic•com>,
Kevin Hilman <khilman@baylibre•com>,
Martin Blumenstingl <martin.blumenstingl@googlemail•com>,
jian.hu@amlogic•com, linux-kernel@vger•kernel.org,
linux-clk@vger•kernel.org, devicetree@vger•kernel.org,
linux-amlogic@lists•infradead.org,
linux-arm-kernel@lists•infradead.org
Subject: Re: [PATCH 00/10] Add support for A9 family clock controller
Date: Tue, 26 May 2026 09:33:14 +0200 [thread overview]
Message-ID: <1jldd662x1.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20260511-b4-a9_clk-v1-0-41cb4071b7c9@amlogic.com> (Jian Hu via's message of "Mon, 11 May 2026 20:47:22 +0800")
On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel•org> wrote:
> There are 4 clock controllers in A9 SoC:
> - SCMI clock controller: these clocks are managed by the
> Trusted Firmware-A(TF-A) and handled through SCMI.
> - PLL clock controller.
> - peripheral clock controller.
> - AO clock controller.
>
> There are reserved register regions placed between individual PLLs, so a
> separate driver is implemented for each PLL, similar to T7.
>
> Compared to previous SoCs PLLs, the A9 PLL controller introduces 4 new features:
> 1.PLL l_detect signal supports active-high configuration.
> Previous A7 and T7 l_detect signals are active-low.
> 2.PLL reset signal supports active-low configuration.
> Previous reset signals are active-high.
> 3.Support POWER_OF_TWO for the PLL pre-divider N;
> the N pre-divider follows the same calculation rule as OD.
> 4.The PLL input path includes an inherent divide-by-2 divider.
>
> Implement the first three features in clk-pll.c (verified on A9 and T7),
> with no impact to PLL logic on existing SoCs. Add a fixed divide-by-2 to
> A9 PLL driver for the fourth feature.
>
> A9 PLL is composed as follows:
>
> PLL
> +---------------------------------+
> | |
> | +--+ |
> in/2 >>---[ /2^N ]-->| | +-----+ |
> | | |------| DCO |----->> out
> | +--------->| | +--v--+ |
> | | +--+ | |
> | | | |
> | +--[ *(M + (F/Fmax) ]<--+ |
> | |
> +---------------------------------+
>
> out = in / 2 * (m + frac / frac_max) / 2^n
>
> Signed-off-by: Jian Hu <jian.hu@amlogic•com>
> ---
> Jian Hu (10):
> dt-bindings: clock: Add Amlogic A9 SCMI clock controller
> dt-bindings: clock: Add Amlogic A9 PLL clock controller
> dt-bindings: clock: Add Amlogic A9 peripherals clock controller
> dt-bindings: clock: Add Amlogic A9 AO clock controller
> clk: amlogic: PLL l_detect signal supports active-high configuration
> clk: amlogic: PLL reset signal supports active-low configuration
> clk: amlogic: Support POWER_OF_TWO for PLL pre-divider
> clk: amlogic: Add A9 PLL clock controller driver
> clk: amlogic: Add A9 peripherals clock controller driver
> clk: amlogic: Add A9 AO clock controller driver
>
> .../bindings/clock/amlogic,a9-aoclkc.yaml | 76 +
> .../clock/amlogic,a9-peripherals-clkc.yaml | 150 ++
> .../bindings/clock/amlogic,a9-pll-clkc.yaml | 110 +
> drivers/clk/meson/Kconfig | 28 +
> drivers/clk/meson/Makefile | 2 +
> drivers/clk/meson/a9-aoclk.c | 494 +++++
> drivers/clk/meson/a9-peripherals.c | 2317 ++++++++++++++++++++
> drivers/clk/meson/a9-pll.c | 831 +++++++
> drivers/clk/meson/clk-pll.c | 79 +-
> drivers/clk/meson/clk-pll.h | 6 +
> include/dt-bindings/clock/amlogic,a9-aoclkc.h | 76 +
> .../clock/amlogic,a9-peripherals-clkc.h | 352 +++
> include/dt-bindings/clock/amlogic,a9-pll-clkc.h | 55 +
> include/dt-bindings/clock/amlogic,a9-scmi-clkc.h | 51 +
> 14 files changed, 4609 insertions(+), 18 deletions(-)
For the next version, please split things up.
There is no hard dependency between the different controllers. This will
ease the review.
The PLL controllers are bringing a new contraints in. The global/static
nature of the controllers is something that has been bothering me for a
while but there was no real reason to address it so far. Please give me
some time to think about. Feel free to re-post the other controllers in the
meantime.
> ---
> base-commit: ca89c88bcf69daca829044c638a8163d5ce47af0
> change-id: 20260511-b4-a9_clk-67652c1ae56e
>
> Best regards,
--
Jerome
next prev parent reply other threads:[~2026-05-26 7:38 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 12:47 [PATCH 00/10] Add support for A9 family clock controller Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 01/10] dt-bindings: clock: Add Amlogic A9 SCMI " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL " Jian Hu via B4 Relay
2026-05-15 8:09 ` Krzysztof Kozlowski
2026-05-22 6:20 ` Jian Hu
2026-05-22 9:16 ` Krzysztof Kozlowski
2026-05-22 11:44 ` Jian Hu
2026-05-11 12:47 ` [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals " Jian Hu via B4 Relay
2026-05-14 16:15 ` Jerome Brunet
2026-05-20 3:16 ` Jian Hu
2026-05-15 8:10 ` Krzysztof Kozlowski
2026-05-22 7:49 ` Jian Hu
2026-05-11 12:47 ` [PATCH 04/10] dt-bindings: clock: Add Amlogic A9 AO " Jian Hu via B4 Relay
2026-05-15 8:10 ` Krzysztof Kozlowski
2026-05-22 8:14 ` Jian Hu
2026-05-11 12:47 ` [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration Jian Hu via B4 Relay
2026-05-11 15:47 ` Brian Masney
2026-05-14 15:13 ` Jerome Brunet
2026-05-20 3:25 ` Jian Hu
2026-05-20 7:24 ` Jerome Brunet
2026-05-20 8:46 ` Jian Hu
2026-05-11 12:47 ` [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration Jian Hu via B4 Relay
2026-05-11 15:21 ` Brian Masney
2026-05-13 3:53 ` Jian Hu
2026-05-14 15:16 ` Jerome Brunet
2026-05-20 3:35 ` Jian Hu
2026-05-11 12:47 ` [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider Jian Hu via B4 Relay
2026-05-11 15:23 ` Brian Masney
2026-05-14 15:11 ` Jerome Brunet
2026-05-20 5:47 ` Jian Hu
2026-05-20 7:35 ` Jerome Brunet
2026-05-26 9:58 ` Jian Hu
2026-05-26 12:27 ` Jerome Brunet
2026-05-29 7:08 ` Jian Hu
2026-05-11 12:47 ` [PATCH 08/10] clk: amlogic: Add A9 PLL clock controller driver Jian Hu via B4 Relay
2026-05-11 15:36 ` Brian Masney
2026-05-13 7:25 ` Jian Hu
2026-05-14 16:12 ` Jerome Brunet
2026-05-20 7:33 ` Jian Hu
2026-05-11 12:47 ` [PATCH 09/10] clk: amlogic: Add A9 peripherals " Jian Hu via B4 Relay
2026-05-11 15:42 ` Brian Masney
2026-05-13 8:50 ` Jian Hu
2026-05-11 12:47 ` [PATCH 10/10] clk: amlogic: Add A9 AO " Jian Hu via B4 Relay
2026-05-11 15:45 ` Brian Masney
2026-05-13 9:19 ` Jian Hu
2026-05-14 16:27 ` Jerome Brunet
2026-05-20 7:37 ` Jian Hu
2026-05-26 7:33 ` Jerome Brunet [this message]
2026-05-26 10:05 ` [PATCH 00/10] Add support for A9 family clock controller Jian Hu
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