From: Jerome Brunet <jbrunet@baylibre•com>
To: Jian Hu <jian.hu@amlogic•com>
Cc: Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel•org>,
Michael Turquette <mturquette@baylibre•com>,
Stephen Boyd <sboyd@kernel•org>, Rob Herring <robh@kernel•org>,
Krzysztof Kozlowski <krzk+dt@kernel•org>,
Conor Dooley <conor+dt@kernel•org>,
Neil Armstrong <neil.armstrong@linaro•org>,
Xianwei Zhao <xianwei.zhao@amlogic•com>,
Kevin Hilman <khilman@baylibre•com>,
Martin Blumenstingl <martin.blumenstingl@googlemail•com>,
linux-kernel@vger•kernel.org, linux-clk@vger•kernel.org,
devicetree@vger•kernel.org, linux-amlogic@lists•infradead.org,
linux-arm-kernel@lists•infradead.org
Subject: Re: [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration
Date: Wed, 20 May 2026 09:24:12 +0200 [thread overview]
Message-ID: <1jwlwy5ysj.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <d023303e-e785-4b60-85cd-c83cc3f890e4@amlogic.com> (Jian Hu's message of "Wed, 20 May 2026 11:25:35 +0800")
On mer. 20 mai 2026 at 11:25, Jian Hu <jian.hu@amlogic•com> wrote:
> On 5/14/2026 11:13 PM, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel•org> wrote:
>>
>>> From: Jian Hu <jian.hu@amlogic•com>
>>>
>>> l_detect controls the enable/disable of the PLL lock-detect module.
>>>
>>> For A9, the l_detect signal is active-high:
>>> 0 -> Disable lock-detect module;
>>> 1 -> Enable lock-detect module.
>>>
>>> Here, a flag CLK_MESON_PLL_L_DETECT_ACTIVE_HIGH is added to handle cases
>>> like A9, where the signal is active-high.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic•com>
>>> ---
>>> drivers/clk/meson/clk-pll.c | 9 +++++++--
>>> drivers/clk/meson/clk-pll.h | 2 ++
>>> 2 files changed, 9 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
>>> index 1ea6579a760f..5a0bd75f85a9 100644
>>> --- a/drivers/clk/meson/clk-pll.c
>>> +++ b/drivers/clk/meson/clk-pll.c
>>> @@ -388,8 +388,13 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
>>> }
>>>
>>> if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
>>> - meson_parm_write(clk->map, &pll->l_detect, 1);
>>> - meson_parm_write(clk->map, &pll->l_detect, 0);
>>> + if (pll->flags & CLK_MESON_PLL_L_DETECT_ACTIVE_HIGH) {
>>> + meson_parm_write(clk->map, &pll->l_detect, 0);
>>> + meson_parm_write(clk->map, &pll->l_detect, 1);
>>> + } else {
>>> + meson_parm_write(clk->map, &pll->l_detect, 1);
>>> + meson_parm_write(clk->map, &pll->l_detect, 0);
>>> + }
>> I'm not a fan of this code duplication.
>> Use the introduced CLK_MESON_PLL_L_DETECT_ACTIVE_HIGH to compute the
>> first value, then flip the bit.
>
>
> Ok, I will update this in the next version.
>
> Here is the updated code:
>
> if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
> meson_parm_write(clk->map, &pll->l_detect,
> !(pll->flags &
> CLK_MESON_PLL_L_DETECT_ACTIVE_HIGH));
> meson_parm_write(clk->map, &pll->l_detect,
> !!(pll->flags &
> CLK_MESON_PLL_L_DETECT_ACTIVE_HIGH));
Please use a variable. Make it clean
> }
>
>>> }
>>>
>>> if (meson_clk_pll_wait_lock(hw))
>>> diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
>>> index 949157fb7bf5..97b7c70376a3 100644
>>> --- a/drivers/clk/meson/clk-pll.h
>>> +++ b/drivers/clk/meson/clk-pll.h
>>> @@ -29,6 +29,8 @@ struct pll_mult_range {
>>>
>>> #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
>>> #define CLK_MESON_PLL_NOINIT_ENABLED BIT(1)
>>> +/* l_detect signal is active-high */
>>> +#define CLK_MESON_PLL_L_DETECT_ACTIVE_HIGH BIT(2)
>>>
>>> struct meson_clk_pll_data {
>>> struct parm en;
>> --
>> Jerome
>
> Best regards,
>
> Jian
--
Jerome
next prev parent reply other threads:[~2026-05-20 7:24 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 12:47 [PATCH 00/10] Add support for A9 family clock controller Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 01/10] dt-bindings: clock: Add Amlogic A9 SCMI " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL " Jian Hu via B4 Relay
2026-05-15 8:09 ` Krzysztof Kozlowski
2026-05-22 6:20 ` Jian Hu
2026-05-22 9:16 ` Krzysztof Kozlowski
2026-05-22 11:44 ` Jian Hu
2026-05-11 12:47 ` [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals " Jian Hu via B4 Relay
2026-05-14 16:15 ` Jerome Brunet
2026-05-20 3:16 ` Jian Hu
2026-05-15 8:10 ` Krzysztof Kozlowski
2026-05-22 7:49 ` Jian Hu
2026-05-11 12:47 ` [PATCH 04/10] dt-bindings: clock: Add Amlogic A9 AO " Jian Hu via B4 Relay
2026-05-15 8:10 ` Krzysztof Kozlowski
2026-05-22 8:14 ` Jian Hu
2026-05-11 12:47 ` [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration Jian Hu via B4 Relay
2026-05-11 15:47 ` Brian Masney
2026-05-14 15:13 ` Jerome Brunet
2026-05-20 3:25 ` Jian Hu
2026-05-20 7:24 ` Jerome Brunet [this message]
2026-05-20 8:46 ` Jian Hu
2026-05-11 12:47 ` [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration Jian Hu via B4 Relay
2026-05-11 15:21 ` Brian Masney
2026-05-13 3:53 ` Jian Hu
2026-05-14 15:16 ` Jerome Brunet
2026-05-20 3:35 ` Jian Hu
2026-05-11 12:47 ` [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider Jian Hu via B4 Relay
2026-05-11 15:23 ` Brian Masney
2026-05-14 15:11 ` Jerome Brunet
2026-05-20 5:47 ` Jian Hu
2026-05-20 7:35 ` Jerome Brunet
2026-05-26 9:58 ` Jian Hu
2026-05-26 12:27 ` Jerome Brunet
2026-05-29 7:08 ` Jian Hu
2026-05-11 12:47 ` [PATCH 08/10] clk: amlogic: Add A9 PLL clock controller driver Jian Hu via B4 Relay
2026-05-11 15:36 ` Brian Masney
2026-05-13 7:25 ` Jian Hu
2026-05-14 16:12 ` Jerome Brunet
2026-05-20 7:33 ` Jian Hu
2026-05-11 12:47 ` [PATCH 09/10] clk: amlogic: Add A9 peripherals " Jian Hu via B4 Relay
2026-05-11 15:42 ` Brian Masney
2026-05-13 8:50 ` Jian Hu
2026-05-11 12:47 ` [PATCH 10/10] clk: amlogic: Add A9 AO " Jian Hu via B4 Relay
2026-05-11 15:45 ` Brian Masney
2026-05-13 9:19 ` Jian Hu
2026-05-14 16:27 ` Jerome Brunet
2026-05-20 7:37 ` Jian Hu
2026-05-26 7:33 ` [PATCH 00/10] Add support for A9 family clock controller Jerome Brunet
2026-05-26 10:05 ` Jian Hu
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