From: Jian Hu <jian.hu@amlogic•com>
To: Jerome Brunet <jbrunet@baylibre•com>,
Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel•org>
Cc: Michael Turquette <mturquette@baylibre•com>,
Stephen Boyd <sboyd@kernel•org>, Rob Herring <robh@kernel•org>,
Krzysztof Kozlowski <krzk+dt@kernel•org>,
Conor Dooley <conor+dt@kernel•org>,
Neil Armstrong <neil.armstrong@linaro•org>,
Xianwei Zhao <xianwei.zhao@amlogic•com>,
Kevin Hilman <khilman@baylibre•com>,
Martin Blumenstingl <martin.blumenstingl@googlemail•com>,
linux-kernel@vger•kernel.org, linux-clk@vger•kernel.org,
devicetree@vger•kernel.org, linux-amlogic@lists•infradead.org,
linux-arm-kernel@lists•infradead.org
Subject: Re: [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration
Date: Wed, 20 May 2026 11:35:28 +0800 [thread overview]
Message-ID: <26738e81-97cf-406a-94e6-b4a02f0b9609@amlogic.com> (raw)
In-Reply-To: <1jmry26my3.fsf@starbuckisacylon.baylibre.com>
On 5/14/2026 11:16 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel•org> wrote:
>
>> From: Jian Hu <jian.hu@amlogic•com>
>>
>> In the A9 design, the PLL reset signal is configured as active-low.
>>
>> Add the flag 'CLK_MESON_PLL_RST_N' to indicate that the PLL reset signal
>> is active-low.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic•com>
>> ---
>> drivers/clk/meson/clk-pll.c | 42 +++++++++++++++++++++++++++++++-----------
>> drivers/clk/meson/clk-pll.h | 2 ++
>> 2 files changed, 33 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
>> index 5a0bd75f85a9..8568ad6ba7b6 100644
>> --- a/drivers/clk/meson/clk-pll.c
>> +++ b/drivers/clk/meson/clk-pll.c
>> @@ -295,10 +295,14 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
>> {
>> struct clk_regmap *clk = to_clk_regmap(hw);
>> struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
>> + unsigned int rst;
>>
>> - if (MESON_PARM_APPLICABLE(&pll->rst) &&
>> - meson_parm_read(clk->map, &pll->rst))
>> - return 0;
>> + if (MESON_PARM_APPLICABLE(&pll->rst)) {
>> + rst = meson_parm_read(clk->map, &pll->rst);
>> + if ((rst && !(pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW)) ||
>> + (!rst && (pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW)))
> Again not a great usage of binary ops. What you've written above is the
> verbose version of a XOR.
>
> The code duplication remarks applies to the rest of the patch too
Ok, I will update this and the other similar instances below in the next
version.
Here is the updated code for it:
int active_low = !!(pll->flags & CLK_MESON_PLL_RST_ACTIVE_LOW);
if (MESON_PARM_APPLICABLE(&pll->rst) &&
(meson_parm_read(clk->map, &pll->rst) ^ active_low))
[...]
Best regards,
Jian
next prev parent reply other threads:[~2026-05-20 3:35 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 12:47 [PATCH 00/10] Add support for A9 family clock controller Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 01/10] dt-bindings: clock: Add Amlogic A9 SCMI " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL " Jian Hu via B4 Relay
2026-05-15 8:09 ` Krzysztof Kozlowski
2026-05-22 6:20 ` Jian Hu
2026-05-22 9:16 ` Krzysztof Kozlowski
2026-05-22 11:44 ` Jian Hu
2026-05-11 12:47 ` [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals " Jian Hu via B4 Relay
2026-05-14 16:15 ` Jerome Brunet
2026-05-20 3:16 ` Jian Hu
2026-05-15 8:10 ` Krzysztof Kozlowski
2026-05-22 7:49 ` Jian Hu
2026-05-11 12:47 ` [PATCH 04/10] dt-bindings: clock: Add Amlogic A9 AO " Jian Hu via B4 Relay
2026-05-15 8:10 ` Krzysztof Kozlowski
2026-05-22 8:14 ` Jian Hu
2026-05-11 12:47 ` [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration Jian Hu via B4 Relay
2026-05-11 15:47 ` Brian Masney
2026-05-14 15:13 ` Jerome Brunet
2026-05-20 3:25 ` Jian Hu
2026-05-20 7:24 ` Jerome Brunet
2026-05-20 8:46 ` Jian Hu
2026-05-11 12:47 ` [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration Jian Hu via B4 Relay
2026-05-11 15:21 ` Brian Masney
2026-05-13 3:53 ` Jian Hu
2026-05-14 15:16 ` Jerome Brunet
2026-05-20 3:35 ` Jian Hu [this message]
2026-05-11 12:47 ` [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider Jian Hu via B4 Relay
2026-05-11 15:23 ` Brian Masney
2026-05-14 15:11 ` Jerome Brunet
2026-05-20 5:47 ` Jian Hu
2026-05-20 7:35 ` Jerome Brunet
2026-05-26 9:58 ` Jian Hu
2026-05-26 12:27 ` Jerome Brunet
2026-05-29 7:08 ` Jian Hu
2026-05-11 12:47 ` [PATCH 08/10] clk: amlogic: Add A9 PLL clock controller driver Jian Hu via B4 Relay
2026-05-11 15:36 ` Brian Masney
2026-05-13 7:25 ` Jian Hu
2026-05-14 16:12 ` Jerome Brunet
2026-05-20 7:33 ` Jian Hu
2026-05-11 12:47 ` [PATCH 09/10] clk: amlogic: Add A9 peripherals " Jian Hu via B4 Relay
2026-05-11 15:42 ` Brian Masney
2026-05-13 8:50 ` Jian Hu
2026-05-11 12:47 ` [PATCH 10/10] clk: amlogic: Add A9 AO " Jian Hu via B4 Relay
2026-05-11 15:45 ` Brian Masney
2026-05-13 9:19 ` Jian Hu
2026-05-14 16:27 ` Jerome Brunet
2026-05-20 7:37 ` Jian Hu
2026-05-26 7:33 ` [PATCH 00/10] Add support for A9 family clock controller Jerome Brunet
2026-05-26 10:05 ` Jian Hu
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