* [PATCH 02/20] dt-bindings: timer: Convert Allwinner A10 Timer to a schema
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 03/20] dt-bindings: timer: Add missing compatibles Daniel Lezcano
` (7 subsequent siblings)
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
From: Maxime Ripard <maxime.ripard@bootlin•com>
The older Allwinner SoCs have a Timer supported in Linux, with a matching
Device Tree binding.
While the original binding only mentions one interrupt, the timer actually
has 6 of them.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin•com>
Reviewed-by: Rob Herring <robh@kernel•org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 76 +++++++++++++++++++
.../bindings/timer/allwinner,sun4i-timer.txt | 19 -----
2 files changed, 76 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
new file mode 100644
index 000000000000..7292a424092c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 Timer Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie•org>
+ - Maxime Ripard <maxime.ripard@bootlin•com>
+
+properties:
+ compatible:
+ enum:
+ - allwinner,sun4i-a10-timer
+ - allwinner,suniv-f1c100s-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ List of timers interrupts
+
+ clocks:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun4i-a10-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ maxItems: 6
+
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,suniv-f1c100s-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ timer {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x400>;
+ interrupts = <22>,
+ <23>,
+ <24>,
+ <25>,
+ <67>,
+ <68>;
+ clocks = <&osc>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
deleted file mode 100644
index 3da9d515c03a..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Allwinner A1X SoCs Timer Controller
-
-Required properties:
-
-- compatible : should be one of the following:
- "allwinner,sun4i-a10-timer"
- "allwinner,suniv-f1c100s-timer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupt of the first timer
-- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-
-Example:
-
-timer {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0x400>;
- interrupts = <22>;
- clocks = <&osc>;
-};
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 03/20] dt-bindings: timer: Add missing compatibles
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
2019-08-26 20:43 ` [PATCH 02/20] dt-bindings: timer: Convert Allwinner A10 Timer to a schema Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 04/20] clocksource: sun4i: " Daniel Lezcano
` (6 subsequent siblings)
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
From: Maxime Ripard <maxime.ripard@bootlin•com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin•com>
Reviewed-by: Rob Herring <robh@kernel•org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 7292a424092c..20adc1c8e9cc 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -14,6 +14,8 @@ properties:
compatible:
enum:
- allwinner,sun4i-a10-timer
+ - allwinner,sun8i-a23-timer
+ - allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
reg:
@@ -39,6 +41,30 @@ allOf:
minItems: 6
maxItems: 6
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-a23-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-v3s-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
- if:
properties:
compatible:
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 04/20] clocksource: sun4i: Add missing compatibles
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
2019-08-26 20:43 ` [PATCH 02/20] dt-bindings: timer: Convert Allwinner A10 Timer to a schema Daniel Lezcano
2019-08-26 20:43 ` [PATCH 03/20] dt-bindings: timer: Add missing compatibles Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 05/20] dt-bindings: timer: Convert Allwinner A13 HSTimer to a schema Daniel Lezcano
` (5 subsequent siblings)
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Maxime Ripard, Chen-Yu Tsai, linux-kernel,
moderated list:ARM/Allwinner sunXi SoC support
From: Maxime Ripard <maxime.ripard@bootlin•com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin•com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro•org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
drivers/clocksource/timer-sun4i.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
index 65f38f6ca714..0ba8155b8287 100644
--- a/drivers/clocksource/timer-sun4i.c
+++ b/drivers/clocksource/timer-sun4i.c
@@ -219,5 +219,9 @@ static int __init sun4i_timer_init(struct device_node *node)
}
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
+ sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
+ sun4i_timer_init);
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
sun4i_timer_init);
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 05/20] dt-bindings: timer: Convert Allwinner A13 HSTimer to a schema
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
` (2 preceding siblings ...)
2019-08-26 20:43 ` [PATCH 04/20] clocksource: sun4i: " Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 06/20] clocksource/drivers/tcb_clksrc: Register delay timer Daniel Lezcano
` (4 subsequent siblings)
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
From: Maxime Ripard <maxime.ripard@bootlin•com>
The newer Allwinner SoCs have a High Speed Timer supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin•com>
Reviewed-by: Rob Herring <robh@kernel•org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
.../timer/allwinner,sun5i-a13-hstimer.txt | 26 ------
.../timer/allwinner,sun5i-a13-hstimer.yaml | 79 +++++++++++++++++++
2 files changed, 79 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
deleted file mode 100644
index 2c5c1be78360..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Allwinner SoCs High Speed Timer Controller
-
-Required properties:
-
-- compatible : should be "allwinner,sun5i-a13-hstimer" or
- "allwinner,sun7i-a20-hstimer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
- one)
-- clocks: phandle to the source clock (usually the AHB clock)
-
-Optional properties:
-- resets: phandle to a reset controller asserting the timer
-
-Example:
-
-timer@1c60000 {
- compatible = "allwinner,sun7i-a20-hstimer";
- reg = <0x01c60000 0x1000>;
- interrupts = <0 51 1>,
- <0 52 1>,
- <0 53 1>,
- <0 54 1>;
- clocks = <&ahb1_gates 19>;
- resets = <&ahb1rst 19>;
-};
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
new file mode 100644
index 000000000000..dfa0c41fd261
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A13 High-Speed Timer Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie•org>
+ - Maxime Ripard <maxime.ripard@bootlin•com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: allwinner,sun5i-a13-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+ - items:
+ - const: allwinner,sun6i-a31-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Timer 0 Interrupt
+ - description: Timer 1 Interrupt
+ - description: Timer 2 Interrupt
+ - description: Timer 3 Interrupt
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun5i-a13-hstimer
+
+then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+else:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@1c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 1>,
+ <0 52 1>,
+ <0 53 1>,
+ <0 54 1>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1rst 19>;
+ };
+
+...
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 06/20] clocksource/drivers/tcb_clksrc: Register delay timer
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
` (3 preceding siblings ...)
2019-08-26 20:43 ` [PATCH 05/20] dt-bindings: timer: Convert Allwinner A13 HSTimer to a schema Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 07/20] clocksource/drivers/imx-sysctr: Add internal clock divider handle Daniel Lezcano
` (3 subsequent siblings)
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches, linux-kernel,
moderated list:ARM/Microchip AT91 SoC support
From: Alexandre Belloni <alexandre.belloni@bootlin•com>
Implement and register delay timer to allow get_cycles() to work properly.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin•com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/timer-atmel-tcb.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5e9317dc3d39..a642c23b2fba 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -429,7 +429,7 @@ config ATMEL_ST
config ATMEL_TCB_CLKSRC
bool "Atmel TC Block timer driver" if COMPILE_TEST
- depends on HAS_IOMEM
+ depends on ARM && HAS_IOMEM
select TIMER_OF if OF
help
Support for Timer Counter Blocks on Atmel SoCs.
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 6ed31f9def7e..7427b07495a8 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -6,6 +6,7 @@
#include <linux/irq.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
@@ -125,6 +126,18 @@ static u64 notrace tc_sched_clock_read32(void)
return tc_get_cycles32(&clksrc);
}
+static struct delay_timer tc_delay_timer;
+
+static unsigned long tc_delay_timer_read(void)
+{
+ return tc_get_cycles(&clksrc);
+}
+
+static unsigned long notrace tc_delay_timer_read32(void)
+{
+ return tc_get_cycles32(&clksrc);
+}
+
#ifdef CONFIG_GENERIC_CLOCKEVENTS
struct tc_clkevt_device {
@@ -432,6 +445,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup ony channel 0 */
tcb_setup_single_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read32;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read32;
} else {
/* we have three clocks no matter what the
* underlying platform supports.
@@ -444,6 +458,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup both channel 0 & 1 */
tcb_setup_dual_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read;
}
/* and away we go! */
@@ -458,6 +473,9 @@ static int __init tcb_clksrc_init(struct device_node *node)
sched_clock_register(tc_sched_clock, 32, divided_rate);
+ tc_delay_timer.freq = divided_rate;
+ register_current_timer_delay(&tc_delay_timer);
+
return 0;
err_unregister_clksrc:
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 07/20] clocksource/drivers/imx-sysctr: Add internal clock divider handle
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
` (4 preceding siblings ...)
2019-08-26 20:43 ` [PATCH 06/20] clocksource/drivers/tcb_clksrc: Register delay timer Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 08/20] arm64: dts: imx8mm: Add system counter node Daniel Lezcano
` (2 subsequent siblings)
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Anson Huang, Shawn Guo, Sascha Hauer, linux-kernel,
NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
From: Anson Huang <Anson.Huang@nxp•com>
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang <Anson.Huang@nxp•com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
drivers/clocksource/timer-imx-sysctr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index fd7d68066efb..b7c80a368a1b 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -20,6 +20,8 @@
#define SYS_CTR_EN 0x1
#define SYS_CTR_IRQ_MASK 0x2
+#define SYS_CTR_CLK_DIV 0x3
+
static void __iomem *sys_ctr_base;
static u32 cmpcr;
@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
if (ret)
return ret;
+ /* system counter clock is divided by 3 internally */
+ to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+
sys_ctr_base = timer_of_base(&to_sysctr);
cmpcr = readl(sys_ctr_base + CMPCR);
cmpcr &= ~SYS_CTR_EN;
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 08/20] arm64: dts: imx8mm: Add system counter node
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
` (5 preceding siblings ...)
2019-08-26 20:43 ` [PATCH 07/20] clocksource/drivers/imx-sysctr: Add internal clock divider handle Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 09/20] arm64: dts: imx8mq: " Daniel Lezcano
2019-08-26 20:43 ` [PATCH 10/20] clocksource/drivers/renesas-ostm: Use DIV_ROUND_CLOSEST() helper Daniel Lezcano
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jacky Bai, Anson Huang, Fabio Estevam, Sascha Hauer, linux-kernel,
Daniel Baluta, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Leonard Crestez, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
From: Anson Huang <Anson.Huang@nxp•com>
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp•com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 232a7412755a..89ef22a8f81e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -510,6 +510,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_24m>;
+ clock-names = "per";
+ };
};
aips3: bus@30800000 {
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 09/20] arm64: dts: imx8mq: Add system counter node
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
` (6 preceding siblings ...)
2019-08-26 20:43 ` [PATCH 08/20] arm64: dts: imx8mm: Add system counter node Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
2019-08-26 20:43 ` [PATCH 10/20] clocksource/drivers/renesas-ostm: Use DIV_ROUND_CLOSEST() helper Daniel Lezcano
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Abel Vesa, Anson Huang, Carlo Caione, Andrey Smirnov,
Fabio Estevam, Sascha Hauer, Angus Ainslie (Purism), linux-kernel,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Shawn Guo,
Guido Günther,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Lucas Stach
From: Anson Huang <Anson.Huang@nxp•com>
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp•com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d09b808eff87..b4529773af51 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -635,6 +635,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_25m>;
+ clock-names = "per";
+ };
};
bus@30800000 { /* AIPS3 */
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 10/20] clocksource/drivers/renesas-ostm: Use DIV_ROUND_CLOSEST() helper
[not found] ` <20190826204407.17759-1-daniel.lezcano@linaro.org>
` (7 preceding siblings ...)
2019-08-26 20:43 ` [PATCH 09/20] arm64: dts: imx8mq: " Daniel Lezcano
@ 2019-08-26 20:43 ` Daniel Lezcano
8 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Alexandre Torgue, Geert Uytterhoeven, linux-kernel,
Maxime Coquelin, moderated list:ARM/STM32 ARCHITECTURE,
moderated list:ARM/STM32 ARCHITECTURE
From: Geert Uytterhoeven <geert+renesas@glider•be>
Use the DIV_ROUND_CLOSEST() helper instead of open-coding the same
operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider•be>
Reviewed-by: Simon Horman <horms+renesas@verge•net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro•org>
---
drivers/clocksource/renesas-ostm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c
index 61d5f3b539ce..37c39b901bb1 100644
--- a/drivers/clocksource/renesas-ostm.c
+++ b/drivers/clocksource/renesas-ostm.c
@@ -221,7 +221,7 @@ static int __init ostm_init(struct device_node *np)
}
rate = clk_get_rate(ostm_clk);
- ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ;
+ ostm->ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
/*
* First probed device will be used as system clocksource. Any
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread