* [PATCH 01/17] coresight: etm4x: Two function calls less
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 02/17] coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996 Mathieu Poirier
` (16 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Markus Elfring <elfring@users•sourceforge.net>
Avoid an extra function call in two function implementations
by using a ternary operator instead of a conditional statement.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users•sourceforge.net>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index a0365e23678e..219c10eb752c 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -296,11 +296,8 @@ static ssize_t mode_store(struct device *dev,
spin_lock(&drvdata->spinlock);
config->mode = val & ETMv4_MODE_ALL;
-
- if (config->mode & ETM_MODE_EXCLUDE)
- etm4_set_mode_exclude(drvdata, true);
- else
- etm4_set_mode_exclude(drvdata, false);
+ etm4_set_mode_exclude(drvdata,
+ config->mode & ETM_MODE_EXCLUDE ? true : false);
if (drvdata->instrp0 == true) {
/* start by clearing instruction P0 field */
@@ -999,10 +996,8 @@ static ssize_t addr_range_store(struct device *dev,
* Program include or exclude control bits for vinst or vdata
* whenever we change addr comparators to ETM_ADDR_TYPE_RANGE
*/
- if (config->mode & ETM_MODE_EXCLUDE)
- etm4_set_mode_exclude(drvdata, true);
- else
- etm4_set_mode_exclude(drvdata, false);
+ etm4_set_mode_exclude(drvdata,
+ config->mode & ETM_MODE_EXCLUDE ? true : false);
spin_unlock(&drvdata->spinlock);
return size;
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 02/17] coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
2019-08-29 20:28 ` [PATCH 01/17] coresight: etm4x: Two function calls less Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 03/17] coresight: cpu-debug: Add support for Qualcomm Kryo Mathieu Poirier
` (15 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora•org>
Instead of overriding the peripheral id(PID) check in AMBA
by hardcoding them in DT, add the PIDs to the ETM4x driver.
Here we use Unique Component Identifier(UCI) for MSM8996
since the ETM and CPU debug module shares the same PIDs.
SDM845 does not support CPU debug module.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora•org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 7bcac8896fc1..28bcc0e58d7a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1192,11 +1192,15 @@ static struct amba_cs_uci_id uci_id_etm4[] = {
};
static const struct amba_id etm4_ids[] = {
- CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
- CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
- CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
- CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
- CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4), /* Cortex-A35 */
+ CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
+ CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
+ CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
+ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
+ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
+ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
+ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
+ CS_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385 Cortex-A55 */
+ CS_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385 Cortex-A75 */
{},
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 03/17] coresight: cpu-debug: Add support for Qualcomm Kryo
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
2019-08-29 20:28 ` [PATCH 01/17] coresight: etm4x: Two function calls less Mathieu Poirier
2019-08-29 20:28 ` [PATCH 02/17] coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996 Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 04/17] coresight: etr_buf: Consolidate refcount initialization Mathieu Poirier
` (14 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora•org>
Add support for coresight CPU debug module on Qualcomm
Kryo CPUs. This patch adds the UCI entries for Kryo CPUs
found on MSM8996 which shares the same PIDs as ETMs.
Without this, below error is observed on MSM8996:
[ 5.429867] OF: graph: no port node found in /soc/debug@3810000
[ 5.429938] coresight-etm4x: probe of 3810000.debug failed with error -22
[ 5.435415] coresight-cpu-debug 3810000.debug: Coresight debug-CPU0 initialized
[ 5.446474] OF: graph: no port node found in /soc/debug@3910000
[ 5.448927] coresight-etm4x: probe of 3910000.debug failed with error -22
[ 5.454681] coresight-cpu-debug 3910000.debug: Coresight debug-CPU1 initialized
[ 5.487765] OF: graph: no port node found in /soc/debug@3a10000
[ 5.488007] coresight-etm4x: probe of 3a10000.debug failed with error -22
[ 5.493024] coresight-cpu-debug 3a10000.debug: Coresight debug-CPU2 initialized
[ 5.501802] OF: graph: no port node found in /soc/debug@3b10000
[ 5.512901] coresight-etm4x: probe of 3b10000.debug failed with error -22
[ 5.513192] coresight-cpu-debug 3b10000.debug: Coresight debug-CPU3 initialized
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora•org>
Tested-by: Leo Yan <leo.yan@linaro•org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
.../hwtracing/coresight/coresight-cpu-debug.c | 33 +++++++++----------
drivers/hwtracing/coresight/coresight-priv.h | 10 +++---
2 files changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
index 2463aa7ab4f6..96544b348c27 100644
--- a/drivers/hwtracing/coresight/coresight-cpu-debug.c
+++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
@@ -646,24 +646,23 @@ static int debug_remove(struct amba_device *adev)
return 0;
}
+static const struct amba_cs_uci_id uci_id_debug[] = {
+ {
+ /* CPU Debug UCI data */
+ .devarch = 0x47706a15,
+ .devarch_mask = 0xfff0ffff,
+ .devtype = 0x00000015,
+ }
+};
+
static const struct amba_id debug_ids[] = {
- { /* Debug for Cortex-A53 */
- .id = 0x000bbd03,
- .mask = 0x000fffff,
- },
- { /* Debug for Cortex-A57 */
- .id = 0x000bbd07,
- .mask = 0x000fffff,
- },
- { /* Debug for Cortex-A72 */
- .id = 0x000bbd08,
- .mask = 0x000fffff,
- },
- { /* Debug for Cortex-A73 */
- .id = 0x000bbd09,
- .mask = 0x000fffff,
- },
- { 0, 0 },
+ CS_AMBA_ID(0x000bbd03), /* Cortex-A53 */
+ CS_AMBA_ID(0x000bbd07), /* Cortex-A57 */
+ CS_AMBA_ID(0x000bbd08), /* Cortex-A72 */
+ CS_AMBA_ID(0x000bbd09), /* Cortex-A73 */
+ CS_AMBA_UCI_ID(0x000f0205, uci_id_debug), /* Qualcomm Kryo */
+ CS_AMBA_UCI_ID(0x000f0211, uci_id_debug), /* Qualcomm Kryo */
+ {},
};
static struct amba_driver debug_driver = {
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 7d401790dd7e..41ae5863104d 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -185,11 +185,11 @@ static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
}
/* coresight AMBA ID, full UCI structure: id table entry. */
-#define CS_AMBA_UCI_ID(pid, uci_ptr) \
- { \
- .id = pid, \
- .mask = 0x000fffff, \
- .data = uci_ptr \
+#define CS_AMBA_UCI_ID(pid, uci_ptr) \
+ { \
+ .id = pid, \
+ .mask = 0x000fffff, \
+ .data = (void *)uci_ptr \
}
/* extract the data value from a UCI structure given amba_id pointer. */
--
2.17.1
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linux-arm-kernel@lists•infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 04/17] coresight: etr_buf: Consolidate refcount initialization
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (2 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 03/17] coresight: cpu-debug: Add support for Qualcomm Kryo Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 05/17] coresight: tmc-etr: Handle memory errors Mathieu Poirier
` (13 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Suzuki K Poulose <suzuki.poulose@arm•com>
We now use refcounts for the etr_buf users. Let us initialize it
while we allocate it.
Cc: Mathieu Poirier <mathieu.poirier@linaro•org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 17006705287a..3116d1f28e66 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -871,6 +871,7 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata,
return ERR_PTR(rc);
}
+ refcount_set(&etr_buf->refcount, 1);
dev_dbg(dev, "allocated buffer of size %ldKB in mode %d\n",
(unsigned long)size >> 10, etr_buf->mode);
return etr_buf;
@@ -1263,8 +1264,6 @@ get_perf_etr_buf_cpu_wide(struct tmc_drvdata *drvdata,
if (IS_ERR(etr_buf))
return etr_buf;
- refcount_set(&etr_buf->refcount, 1);
-
/* Now that we have a buffer, add it to the IDR. */
mutex_lock(&drvdata->idr_mutex);
ret = idr_alloc(&drvdata->idr, etr_buf, pid, pid + 1, GFP_KERNEL);
@@ -1291,19 +1290,11 @@ get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata,
struct perf_event *event, int nr_pages,
void **pages, bool snapshot)
{
- struct etr_buf *etr_buf;
-
/*
* In per-thread mode the etr_buf isn't shared, so just go ahead
* with memory allocation.
*/
- etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot);
- if (IS_ERR(etr_buf))
- goto out;
-
- refcount_set(&etr_buf->refcount, 1);
-out:
- return etr_buf;
+ return alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot);
}
static struct etr_buf *
--
2.17.1
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linux-arm-kernel@lists•infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 05/17] coresight: tmc-etr: Handle memory errors
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (3 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 04/17] coresight: etr_buf: Consolidate refcount initialization Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 06/17] coresight: tmc-etr: Check if non-secure access is enabled Mathieu Poirier
` (12 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Suzuki K Poulose <suzuki.poulose@arm•com>
We have so far ignored the memory errors, assuming that we have perfect
hardware and driver. Let us handle the memory errors reported by the
TMC ETR in status and truncate the buffer.
Cc: Mathieu Poirier <mathieu.poirier@linaro•org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm•com>
[Removed ASCII smiley face from changelog]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 +++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 3116d1f28e66..2246c1e6744a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -928,6 +928,19 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
rrp = tmc_read_rrp(drvdata);
rwp = tmc_read_rwp(drvdata);
status = readl_relaxed(drvdata->base + TMC_STS);
+
+ /*
+ * If there were memory errors in the session, truncate the
+ * buffer.
+ */
+ if (WARN_ON_ONCE(status & TMC_STS_MEMERR)) {
+ dev_dbg(&drvdata->csdev->dev,
+ "tmc memory error detected, truncating buffer\n");
+ etr_buf->len = 0;
+ etr_buf->full = 0;
+ return;
+ }
+
etr_buf->full = status & TMC_STS_FULL;
WARN_ON(!etr_buf->ops || !etr_buf->ops->sync);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 1ed50411cc3c..95d2e2747970 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -47,6 +47,7 @@
#define TMC_STS_TMCREADY_BIT 2
#define TMC_STS_FULL BIT(0)
#define TMC_STS_TRIGGERED BIT(1)
+#define TMC_STS_MEMERR BIT(5)
/*
* TMC_AXICTL - 0x110
*
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 06/17] coresight: tmc-etr: Check if non-secure access is enabled
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (4 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 05/17] coresight: tmc-etr: Handle memory errors Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 07/17] coresight: Convert pr_warn to dev_warn for obsolete bindings Mathieu Poirier
` (11 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Suzuki K Poulose <suzuki.poulose@arm•com>
CoreSight TMC-ETR must have the non-secure invasive debug access
enabled for use by self-hosted tracing. Without it, there is no
point in enabling the ETR. So, let us check it in the TMC_AUTHSTATUS
register and fail the probe if it is disabled.
Cc: Mathieu Poirier <mathieu.poirier@linaro•org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-tmc.c | 12 ++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 3 +++
2 files changed, 15 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index be37aff573b4..3055bf8e2236 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -236,6 +236,7 @@ coresight_tmc_reg(ffcr, TMC_FFCR);
coresight_tmc_reg(mode, TMC_MODE);
coresight_tmc_reg(pscr, TMC_PSCR);
coresight_tmc_reg(axictl, TMC_AXICTL);
+coresight_tmc_reg(authstatus, TMC_AUTHSTATUS);
coresight_tmc_reg(devid, CORESIGHT_DEVID);
coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
@@ -255,6 +256,7 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
&dev_attr_devid.attr,
&dev_attr_dba.attr,
&dev_attr_axictl.attr,
+ &dev_attr_authstatus.attr,
NULL,
};
@@ -342,6 +344,13 @@ static inline bool tmc_etr_can_use_sg(struct device *dev)
return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
}
+static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
+{
+ u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS);
+
+ return (auth & TMC_AUTH_NSID_MASK) == 0x3;
+}
+
/* Detect and initialise the capabilities of a TMC ETR */
static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
{
@@ -349,6 +358,9 @@ static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
u32 dma_mask = 0;
struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
+ if (!tmc_etr_has_non_secure_access(drvdata))
+ return -EACCES;
+
/* Set the unadvertised capabilities */
tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 95d2e2747970..4c59f2a4ad0e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -39,6 +39,7 @@
#define TMC_ITATBCTR2 0xef0
#define TMC_ITATBCTR1 0xef4
#define TMC_ITATBCTR0 0xef8
+#define TMC_AUTHSTATUS 0xfb8
/* register description */
/* TMC_CTL - 0x020 */
@@ -90,6 +91,8 @@
#define TMC_DEVID_AXIAW_SHIFT 17
#define TMC_DEVID_AXIAW_MASK 0x7f
+#define TMC_AUTH_NSID_MASK GENMASK(1, 0)
+
enum tmc_config_type {
TMC_CONFIG_TYPE_ETB,
TMC_CONFIG_TYPE_ETR,
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 07/17] coresight: Convert pr_warn to dev_warn for obsolete bindings
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (5 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 06/17] coresight: tmc-etr: Check if non-secure access is enabled Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 08/17] coresight: acpi: Static funnel support Mathieu Poirier
` (10 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Suzuki K Poulose <suzuki.poulose@arm•com>
We warn the users of obsolete bindings in the DT for coresight replicator
and funnel drivers. However we use pr_warn_once() which doesn't give a clue
about which device it is bound to. Let us use dev_warn_once() to give the
context.
Cc: Mathieu Poirier <mathieu.poirier@linaro•org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-funnel.c | 2 +-
drivers/hwtracing/coresight/coresight-replicator.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index fa97cb9ab4f9..84ca30f4e5ec 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -192,7 +192,7 @@ static int funnel_probe(struct device *dev, struct resource *res)
if (is_of_node(dev_fwnode(dev)) &&
of_device_is_compatible(dev->of_node, "arm,coresight-funnel"))
- pr_warn_once("Uses OBSOLETE CoreSight funnel binding\n");
+ dev_warn_once(dev, "Uses OBSOLETE CoreSight funnel binding\n");
desc.name = coresight_alloc_device_name(&funnel_devs, dev);
if (!desc.name)
diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index b7d6d59d56db..b29ba640eb25 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -184,7 +184,8 @@ static int replicator_probe(struct device *dev, struct resource *res)
if (is_of_node(dev_fwnode(dev)) &&
of_device_is_compatible(dev->of_node, "arm,coresight-replicator"))
- pr_warn_once("Uses OBSOLETE CoreSight replicator binding\n");
+ dev_warn_once(dev,
+ "Uses OBSOLETE CoreSight replicator binding\n");
desc.name = coresight_alloc_device_name(&replicator_devs, dev);
if (!desc.name)
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 08/17] coresight: acpi: Static funnel support
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (6 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 07/17] coresight: Convert pr_warn to dev_warn for obsolete bindings Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 09/17] coresight: etm4x: Remove superfluous setting of os_unlock Mathieu Poirier
` (9 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Suzuki K Poulose <suzuki.poulose@arm•com>
The ACPI bindings for CoreSight has been updated to add the device
id for non-programmable CoreSight funnels (aka static funnels) as of
v1.1 [0]. Add the ACPI id for static funnels in the driver.
[0] https://static.docs.arm.com/den0067/a/DEN0067_CoreSight_ACPI_1.1.pdf
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-funnel.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index 84ca30f4e5ec..05f7896c3a01 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -5,6 +5,7 @@
* Description: CoreSight Funnel driver
*/
+#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
@@ -302,11 +303,19 @@ static const struct of_device_id static_funnel_match[] = {
{}
};
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id static_funnel_ids[] = {
+ {"ARMHC9FE", 0},
+ {},
+};
+#endif
+
static struct platform_driver static_funnel_driver = {
.probe = static_funnel_probe,
.driver = {
.name = "coresight-static-funnel",
.of_match_table = static_funnel_match,
+ .acpi_match_table = ACPI_PTR(static_funnel_ids),
.pm = &funnel_dev_pm_ops,
.suppress_bind_attrs = true,
},
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 09/17] coresight: etm4x: Remove superfluous setting of os_unlock
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (7 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 08/17] coresight: acpi: Static funnel support Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 10/17] coresight: etm4x: Use explicit barriers on enable/disable Mathieu Poirier
` (8 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Andrew Murray <andrew.murray@arm•com>
In addition to unlocking the OS lock, etm4_os_unlock will also
set the os_unlock flag. Therefore let's avoid unnecessarily
setting os_unlock flag outside of this function.
Signed-off-by: Andrew Murray <andrew.murray@arm•com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm•com>
[Fixed capital letter for "remove" in the title]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 28bcc0e58d7a..7ad15651e069 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1047,10 +1047,8 @@ static int etm4_starting_cpu(unsigned int cpu)
return 0;
spin_lock(&etmdrvdata[cpu]->spinlock);
- if (!etmdrvdata[cpu]->os_unlock) {
+ if (!etmdrvdata[cpu]->os_unlock)
etm4_os_unlock(etmdrvdata[cpu]);
- etmdrvdata[cpu]->os_unlock = true;
- }
if (local_read(&etmdrvdata[cpu]->mode))
etm4_enable_hw(etmdrvdata[cpu]);
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 10/17] coresight: etm4x: Use explicit barriers on enable/disable
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (8 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 09/17] coresight: etm4x: Remove superfluous setting of os_unlock Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 11/17] coresight: etm4x: use module_param instead of module_param_named Mathieu Poirier
` (7 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Andrew Murray <andrew.murray@arm•com>
Synchronization is recommended before disabling the trace registers
to prevent any start or stop points being speculative at the point
of disabling the unit (section 7.3.77 of ARM IHI 0064D).
Synchronization is also recommended after programming the trace
registers to ensure all updates are committed prior to normal code
resuming (section 4.3.7 of ARM IHI 0064D).
Let's ensure these syncronization points are present in the code
and clearly commented.
Note that we could rely on the barriers in CS_LOCK and
coresight_disclaim_device_unlocked or the context switch to user
space - however coresight may be of use in the kernel.
On armv8 the mb macro is defined as dsb(sy) - Given that the etm4x is
only used on armv8 let's directly use dsb(sy) instead of mb(). This
removes some ambiguity and makes it easier to correlate the code with
the TRM.
Signed-off-by: Andrew Murray <andrew.murray@arm•com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm•com>
[Fixed capital letter for "use" in title]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 7ad15651e069..ec9468880c71 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -188,6 +188,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
dev_err(etm_dev,
"timeout while waiting for Idle Trace Status\n");
+ /*
+ * As recommended by section 4.3.7 ("Synchronization when using the
+ * memory-mapped interface") of ARM IHI 0064D
+ */
+ dsb(sy);
+ isb();
+
done:
CS_LOCK(drvdata->base);
@@ -453,8 +460,12 @@ static void etm4_disable_hw(void *info)
/* EN, bit[0] Trace unit enable bit */
control &= ~0x1;
- /* make sure everything completes before disabling */
- mb();
+ /*
+ * Make sure everything completes before disabling, as recommended
+ * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
+ * SSTATUS") of ARM IHI 0064D
+ */
+ dsb(sy);
isb();
writel_relaxed(control, drvdata->base + TRCPRGCTLR);
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 11/17] coresight: etm4x: use module_param instead of module_param_named
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (9 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 10/17] coresight: etm4x: Use explicit barriers on enable/disable Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 12/17] coresight: etm4x: improve clarity of etm4_os_unlock comment Mathieu Poirier
` (6 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Andrew Murray <andrew.murray@arm•com>
Given that the user-exposed module parameter for 'boot_enable' matches
the variable that it sets, let's use module_param instead of
module_param_named.
Let's also use octal permissions (checkpatch recommends this) and
provide a module parameter description.
Signed-off-by: Andrew Murray <andrew.murray@arm•com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index ec9468880c71..615bdbf7c9b7 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -34,7 +34,8 @@
#include "coresight-etm-perf.h"
static int boot_enable;
-module_param_named(boot_enable, boot_enable, int, S_IRUGO);
+module_param(boot_enable, int, 0444);
+MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
/* The number of ETMv4 currently registered */
static int etm4_count;
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 12/17] coresight: etm4x: improve clarity of etm4_os_unlock comment
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (10 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 11/17] coresight: etm4x: use module_param instead of module_param_named Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 13/17] coresight: tmc-etr: Fix updating buffer in not-snapshot mode Mathieu Poirier
` (5 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Andrew Murray <andrew.murray@arm•com>
To improve clarity, let's update the comment for etm4_os_unlock
to use the name of the register as per the ETM architecture
specification.
The existing comment is also misleading as it suggests any value
written to TRCOSLAR unlocks the trace registers, however it must
be '0' - let's also correct this.
Signed-off-by: Andrew Murray <andrew.murray@arm•com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 615bdbf7c9b7..a128b5063f46 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -48,7 +48,7 @@ static enum cpuhp_state hp_online;
static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
{
- /* Writing any value to ETMOSLAR unlocks the trace registers */
+ /* Writing 0 to TRCOSLAR unlocks the trace registers */
writel_relaxed(0x0, drvdata->base + TRCOSLAR);
drvdata->os_unlock = true;
isb();
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 13/17] coresight: tmc-etr: Fix updating buffer in not-snapshot mode.
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (11 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 12/17] coresight: etm4x: improve clarity of etm4_os_unlock comment Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 14/17] coresight: tmc-etr: Fix perf_data check Mathieu Poirier
` (4 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Yabin Cui <yabinc@google•com>
TMC etr always copies all available data to perf aux buffer, which
may exceed the available space in perf aux buffer. It isn't suitable
for not-snapshot mode, because:
1) It may overwrite previously written data.
2) It may make the perf_event_mmap_page->aux_head report having more
or less data than the reality.
So change to only copy the latest data fitting the available space in
perf aux buffer.
Signed-off-by: Yabin Cui <yabinc@google•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2246c1e6744a..f835a3c78b37 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1414,9 +1414,10 @@ static void tmc_free_etr_buffer(void *config)
* tmc_etr_sync_perf_buffer: Copy the actual trace data from the hardware
* buffer to the perf ring buffer.
*/
-static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
+static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
+ unsigned long to_copy)
{
- long bytes, to_copy;
+ long bytes;
long pg_idx, pg_offset, src_offset;
unsigned long head = etr_perf->head;
char **dst_pages, *src_buf;
@@ -1426,8 +1427,7 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
pg_idx = head >> PAGE_SHIFT;
pg_offset = head & (PAGE_SIZE - 1);
dst_pages = (char **)etr_perf->pages;
- src_offset = etr_buf->offset;
- to_copy = etr_buf->len;
+ src_offset = etr_buf->offset + etr_buf->len - to_copy;
while (to_copy > 0) {
/*
@@ -1438,6 +1438,8 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
* 3) what is available in the destination page.
* in one iteration.
*/
+ if (src_offset >= etr_buf->size)
+ src_offset -= etr_buf->size;
bytes = tmc_etr_buf_get_data(etr_buf, src_offset, to_copy,
&src_buf);
if (WARN_ON_ONCE(bytes <= 0))
@@ -1458,8 +1460,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
/* Move source pointers */
src_offset += bytes;
- if (src_offset >= etr_buf->size)
- src_offset -= etr_buf->size;
}
}
@@ -1505,7 +1505,11 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
spin_unlock_irqrestore(&drvdata->spinlock, flags);
size = etr_buf->len;
- tmc_etr_sync_perf_buffer(etr_perf);
+ if (!etr_perf->snapshot && size > handle->size) {
+ size = handle->size;
+ lost = true;
+ }
+ tmc_etr_sync_perf_buffer(etr_perf, size);
/*
* In snapshot mode we simply increment the head by the number of byte
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 14/17] coresight: tmc-etr: Fix perf_data check
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (12 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 13/17] coresight: tmc-etr: Fix updating buffer in not-snapshot mode Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 15/17] coresight: tmc: Make memory width mask computation into a function Mathieu Poirier
` (3 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Yabin Cui <yabinc@google•com>
When tracing etm data of multiple threads on multiple cpus through
perf interface, each cpu has a unique etr_perf_buffer while sharing
the same etr device. There is no guarantee that the last cpu starts
etm tracing also stops last. This makes perf_data check fail.
Fix it by checking etr_buf instead of etr_perf_buffer.
Also move the code setting and clearing perf_buf to more suitable
places.
Fixes: 3147da92a8a8 ("coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios")
Signed-off-by: Yabin Cui <yabinc@google•com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 8 ++++----
drivers/hwtracing/coresight/coresight-tmc.h | 6 +++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index f835a3c78b37..4f000a03152e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1488,7 +1488,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
goto out;
}
- if (WARN_ON(drvdata->perf_data != etr_perf)) {
+ if (WARN_ON(drvdata->perf_buf != etr_buf)) {
lost = true;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
goto out;
@@ -1500,8 +1500,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
tmc_sync_etr_buf(drvdata);
CS_LOCK(drvdata->base);
- /* Reset perf specific data */
- drvdata->perf_data = NULL;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
size = etr_buf->len;
@@ -1564,7 +1562,6 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
}
etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
- drvdata->perf_data = etr_perf;
/*
* No HW configuration is needed if the sink is already in
@@ -1580,6 +1577,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
/* Associate with monitored process. */
drvdata->pid = pid;
drvdata->mode = CS_MODE_PERF;
+ drvdata->perf_buf = etr_perf->etr_buf;
atomic_inc(csdev->refcnt);
}
@@ -1625,6 +1623,8 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev)
/* Dissociate from monitored process. */
drvdata->pid = -1;
drvdata->mode = CS_MODE_DISABLED;
+ /* Reset perf specific data */
+ drvdata->perf_buf = NULL;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 4c59f2a4ad0e..9dbcdf453e22 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -182,8 +182,8 @@ struct etr_buf {
* device configuration register (DEVID)
* @idr: Holds etr_bufs allocated for this ETR.
* @idr_mutex: Access serialisation for idr.
- * @perf_data: PERF buffer for ETR.
- * @sysfs_data: SYSFS buffer for ETR.
+ * @sysfs_buf: SYSFS buffer for ETR.
+ * @perf_buf: PERF buffer for ETR.
*/
struct tmc_drvdata {
void __iomem *base;
@@ -206,7 +206,7 @@ struct tmc_drvdata {
struct idr idr;
struct mutex idr_mutex;
struct etr_buf *sysfs_buf;
- void *perf_data;
+ struct etr_buf *perf_buf;
};
struct etr_buf_operations {
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 15/17] coresight: tmc: Make memory width mask computation into a function
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (13 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 14/17] coresight: tmc-etr: Fix perf_data check Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 16/17] coresight: tmc-etr: Decouple buffer sync and barrier packet insertion Mathieu Poirier
` (2 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
Make the computation of a memory mask representing the width of the memory
bus into a function so that it can be re-used by the ETR driver.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
Reviewed-by: Leo Yan <leo.yan@linaro•org>
---
.../hwtracing/coresight/coresight-tmc-etf.c | 23 ++-------------
drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 23b7ff00af5c..807416b75ecc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
* traces.
*/
if (!buf->snapshot && to_read > handle->size) {
- u32 mask = 0;
-
- /*
- * The value written to RRP must be byte-address aligned to
- * the width of the trace memory databus _and_ to a frame
- * boundary (16 byte), whichever is the biggest. For example,
- * for 32-bit, 64-bit and 128-bit wide trace memory, the four
- * LSBs must be 0s. For 256-bit wide trace memory, the five
- * LSBs must be 0s.
- */
- switch (drvdata->memwidth) {
- case TMC_MEM_INTF_WIDTH_32BITS:
- case TMC_MEM_INTF_WIDTH_64BITS:
- case TMC_MEM_INTF_WIDTH_128BITS:
- mask = GENMASK(31, 4);
- break;
- case TMC_MEM_INTF_WIDTH_256BITS:
- mask = GENMASK(31, 5);
- break;
- }
+ u32 mask = tmc_get_memwidth_mask(drvdata);
/*
* Make sure the new size is aligned in accordance with the
- * requirement explained above.
+ * requirement explained in function tmc_get_memwidth_mask().
*/
to_read = handle->size & mask;
/* Move the RAM read pointer up */
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 3055bf8e2236..1cf82fa58289 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(0x0, drvdata->base + TMC_CTL);
}
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
+{
+ u32 mask = 0;
+
+ /*
+ * When moving RRP or an offset address forward, the new values must
+ * be byte-address aligned to the width of the trace memory databus
+ * _and_ to a frame boundary (16 byte), whichever is the biggest. For
+ * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
+ * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
+ * be 0s.
+ */
+ switch (drvdata->memwidth) {
+ case TMC_MEM_INTF_WIDTH_32BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_64BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_128BITS:
+ mask = GENMASK(31, 4);
+ break;
+ case TMC_MEM_INTF_WIDTH_256BITS:
+ mask = GENMASK(31, 5);
+ break;
+ }
+
+ return mask;
+}
+
static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 9dbcdf453e22..71de978575f3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
void tmc_enable_hw(struct tmc_drvdata *drvdata);
void tmc_disable_hw(struct tmc_drvdata *drvdata);
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
/* ETB/ETF functions */
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 16/17] coresight: tmc-etr: Decouple buffer sync and barrier packet insertion
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (14 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 15/17] coresight: tmc: Make memory width mask computation into a function Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-08-29 20:28 ` [PATCH 17/17] coresight: tmc-etr: Add barrier packets when moving offset forward Mathieu Poirier
2019-09-03 20:02 ` [PATCH 00/17] coresight: next v5.3-rc6 Greg KH
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
If less space is available in the perf ring buffer than the ETR buffer,
barrier packets inserted in the trace stream by tmc_sync_etr_buf() are
skipped over when the head of the buffer is moved forward, resulting in
traces that can't be decoded.
This patch decouples the process of syncing ETR buffers and the addition
of barrier packets in order to perform the latter once the offset in the
trace buffer has been properly computed.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
Reviewed-by: Leo Yan <leo.yan@linaro•org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 4f000a03152e..bae47272de98 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -946,10 +946,6 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
WARN_ON(!etr_buf->ops || !etr_buf->ops->sync);
etr_buf->ops->sync(etr_buf, rrp, rwp);
-
- /* Insert barrier packets at the beginning, if there was an overflow */
- if (etr_buf->full)
- tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
@@ -1086,6 +1082,13 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
drvdata->sysfs_buf = NULL;
} else {
tmc_sync_etr_buf(drvdata);
+ /*
+ * Insert barrier packets at the beginning, if there was
+ * an overflow.
+ */
+ if (etr_buf->full)
+ tmc_etr_buf_insert_barrier_packet(etr_buf,
+ etr_buf->offset);
}
}
@@ -1502,11 +1505,16 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
CS_LOCK(drvdata->base);
spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ lost = etr_buf->full;
size = etr_buf->len;
if (!etr_perf->snapshot && size > handle->size) {
size = handle->size;
lost = true;
}
+
+ /* Insert barrier packets at the beginning, if there was an overflow */
+ if (lost)
+ tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
tmc_etr_sync_perf_buffer(etr_perf, size);
/*
@@ -1517,8 +1525,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
*/
if (etr_perf->snapshot)
handle->head += size;
-
- lost |= etr_buf->full;
out:
/*
* Don't set the TRUNCATED flag in snapshot mode because 1) the
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 17/17] coresight: tmc-etr: Add barrier packets when moving offset forward
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (15 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 16/17] coresight: tmc-etr: Decouple buffer sync and barrier packet insertion Mathieu Poirier
@ 2019-08-29 20:28 ` Mathieu Poirier
2019-09-03 20:02 ` [PATCH 00/17] coresight: next v5.3-rc6 Greg KH
17 siblings, 0 replies; 19+ messages in thread
From: Mathieu Poirier @ 2019-08-29 20:28 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
This patch adds barrier packets in the trace stream when the offset in the
data buffer needs to be moved forward. Otherwise the decoder isn't aware
of the break in the stream and can't synchronise itself with the trace
data.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro•org>
Tested-by: Yabin Cui <yabinc@google•com>
Reviewed-by: Leo Yan <leo.yan@linaro•org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 29 +++++++++++++++----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index bae47272de98..625882bc8b08 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1418,10 +1418,11 @@ static void tmc_free_etr_buffer(void *config)
* buffer to the perf ring buffer.
*/
static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
+ unsigned long src_offset,
unsigned long to_copy)
{
long bytes;
- long pg_idx, pg_offset, src_offset;
+ long pg_idx, pg_offset;
unsigned long head = etr_perf->head;
char **dst_pages, *src_buf;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1430,7 +1431,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
pg_idx = head >> PAGE_SHIFT;
pg_offset = head & (PAGE_SIZE - 1);
dst_pages = (char **)etr_perf->pages;
- src_offset = etr_buf->offset + etr_buf->len - to_copy;
while (to_copy > 0) {
/*
@@ -1478,7 +1478,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
void *config)
{
bool lost = false;
- unsigned long flags, size = 0;
+ unsigned long flags, offset, size = 0;
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etr_perf_buffer *etr_perf = config;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1506,16 +1506,35 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
spin_unlock_irqrestore(&drvdata->spinlock, flags);
lost = etr_buf->full;
+ offset = etr_buf->offset;
size = etr_buf->len;
+
+ /*
+ * The ETR buffer may be bigger than the space available in the
+ * perf ring buffer (handle->size). If so advance the offset so that we
+ * get the latest trace data. In snapshot mode none of that matters
+ * since we are expected to clobber stale data in favour of the latest
+ * traces.
+ */
if (!etr_perf->snapshot && size > handle->size) {
- size = handle->size;
+ u32 mask = tmc_get_memwidth_mask(drvdata);
+
+ /*
+ * Make sure the new size is aligned in accordance with the
+ * requirement explained in function tmc_get_memwidth_mask().
+ */
+ size = handle->size & mask;
+ offset = etr_buf->offset + etr_buf->len - size;
+
+ if (offset >= etr_buf->size)
+ offset -= etr_buf->size;
lost = true;
}
/* Insert barrier packets at the beginning, if there was an overflow */
if (lost)
tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
- tmc_etr_sync_perf_buffer(etr_perf, size);
+ tmc_etr_sync_perf_buffer(etr_perf, offset, size);
/*
* In snapshot mode we simply increment the head by the number of byte
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 00/17] coresight: next v5.3-rc6
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
` (16 preceding siblings ...)
2019-08-29 20:28 ` [PATCH 17/17] coresight: tmc-etr: Add barrier packets when moving offset forward Mathieu Poirier
@ 2019-09-03 20:02 ` Greg KH
17 siblings, 0 replies; 19+ messages in thread
From: Greg KH @ 2019-09-03 20:02 UTC (permalink / raw)
To: Mathieu Poirier; +Cc: linux-arm-kernel
On Thu, Aug 29, 2019 at 02:28:25PM -0600, Mathieu Poirier wrote:
> Good afternoon,
>
> Please consider the following for inclusion in the v5.4 cycle.
>
> Applies correctly to the char-misc-next (d4e34999a757) branch.
All now queued up,t hanks.
greg k-h
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^ permalink raw reply [flat|nested] 19+ messages in thread