From: Stephen Boyd <sboyd@kernel•org>
To: Chanwoo Choi <cw00.choi@samsung•com>,
Leonard Crestez <leonard.crestez@nxp•com>,
Rob Herring <robh+dt@kernel•org>
Cc: Mark Rutland <mark.rutland@arm•com>,
Artur Świgoń <a.swigon@partner•samsung.com>,
Jacky Bai <ping.bai@nxp•com>,
Viresh Kumar <viresh.kumar@linaro•org>,
Michael Turquette <mturquette@baylibre•com>,
Angus Ainslie <angus@akkea•ca>,
Alexandre Bailon <abailon@baylibre•com>,
Matthias Kaehlcke <mka@chromium•org>,
Abel Vesa <abel.vesa@nxp•com>,
Saravana Kannan <saravanak@google•com>,
Krzysztof Kozlowski <krzk@kernel•org>,
linux-clk@vger•kernel.org,
MyungJoo Ham <myungjoo.ham@samsung•com>,
linux-imx@nxp•com, devicetree@vger•kernel.org,
linux-pm@vger•kernel.org, Martin Kepplinger <martink@posteo•de>,
Silvano di Ninno <silvano.dininno@nxp•com>,
linux-arm-kernel@lists•infradead.org,
Dong Aisheng <aisheng.dong@nxp•com>,
Anson Huang <Anson.Huang@nxp•com>,
"Rafael J. Wysocki" <rjw@rjwysocki•net>,
Kyungmin Park <kyungmin.park@samsung•com>,
kernel@pengutronix•de, Fabio Estevam <fabio.estevam@nxp•com>,
Shawn Guo <shawnguo@kernel•org>,
Georgi Djakov <georgi.djakov@linaro•org>
Subject: Re: [PATCH v7 2/5] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE
Date: Sun, 24 Nov 2019 17:26:23 -0800 [thread overview]
Message-ID: <20191125012623.D9C482071A@mail.kernel.org> (raw)
In-Reply-To: <9d986ef7a3cb379cea59616ad18e96e3245cbaba.1574458460.git.leonard.crestez@nxp.com>
Quoting Leonard Crestez (2019-11-22 13:45:01)
> DRAM frequency switches are executed in firmware and can change the
> configuration of the DRAM PLL outside linux. Mark these CLKs with
> CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and
> recalculate rates.
>
> In current DRAM frequency tables on 8mm/8mn only the maximum frequency
> uses the PLL so it's always configured in the same way. However reading
> back the PLL configuration is the correct behavior and allows additional
> setpoints in the future.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp•com>
> Reviewed-by: Abel Vesa <abel.vesa@nxp•com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel•org>
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next prev parent reply other threads:[~2019-11-25 1:26 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-22 21:44 [PATCH v7 0/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller Leonard Crestez
2019-11-22 21:45 ` [PATCH v7 1/5] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez
2019-11-25 1:25 ` Stephen Boyd
2019-12-09 1:15 ` Shawn Guo
2019-11-22 21:45 ` [PATCH v7 2/5] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez
2019-11-25 1:26 ` Stephen Boyd [this message]
2019-12-09 1:16 ` Shawn Guo
2019-11-22 21:45 ` [PATCH v7 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller Leonard Crestez
2019-11-22 21:45 ` [PATCH v7 4/5] PM / devfreq: Add dynamic scaling " Leonard Crestez
2019-11-24 23:59 ` Chanwoo Choi
2019-11-26 19:44 ` Rob Herring
2019-11-26 23:25 ` Chanwoo Choi
2019-11-22 21:45 ` [PATCH v7 5/5] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez
2019-11-28 14:43 ` Adam Ford
2019-11-29 5:33 ` Leonard Crestez
2019-12-09 1:34 ` Shawn Guo
2019-12-18 13:35 ` [PATCH v7 0/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller Adam Ford
2019-12-18 14:44 ` Leonard Crestez
2019-12-18 15:05 ` Adam Ford
2019-12-18 15:16 ` Leonard Crestez
2019-12-18 15:37 ` Adam Ford
2019-12-18 16:22 ` Leonard Crestez
2019-12-18 16:42 ` Adam Ford
[not found] ` <CAHCN7xKjpN_XEGLj-1jMG5mBbF=su67k+10frheLt+L1XaR0-g@mail.gmail.com>
2020-01-13 23:36 ` Leonard Crestez
2020-01-15 20:09 ` Adam Ford
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