* [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO
@ 2026-03-27 11:46 Peter Chen
2026-03-30 7:56 ` Krzysztof Kozlowski
2026-05-21 15:23 ` Krzysztof Kozlowski
0 siblings, 2 replies; 4+ messages in thread
From: Peter Chen @ 2026-03-27 11:46 UTC (permalink / raw)
To: arnd
Cc: krzysztof.kozlowski, geert+renesas, linux-kernel,
linux-arm-kernel, cix-kernel-upstream, Peter Chen, Yunseong Kim
Enable the CIX Sky1 pinctrl driver (PINCTRL_SKY1), CIX Sky1 PCIe host
controller (PCI_SKY1_HOST), and Cadence GPIO controller (GPIO_CADENCE)
for the Radxa Orion O6 board which uses the CIX Sky1 SoC.
The pinctrl driver is a dependency for other on-SoC peripherals. The
Cadence-based PCIe host controller enables use of PCIe peripherals on
the board. The Cadence GPIO controller provides GPIO support for the
SoC.
Cc: Yunseong Kim <ysk@kzalloc•com>
Signed-off-by: Peter Chen <peter.chen@cixtech•com>
---
Changes for v3:
- Use specific driver names (CIX Sky1 pinctrl, CIX Sky1 PCIe host
controller, Cadence GPIO) in subject and commit message instead of
generic terms.
- Remove external Debian bug reference; explain rationale directly.
- Remove NVMe mention since only PCIe host controller is enabled.
Changes for v2:
- Delete CIX HDA configurations due to it is not used at current
Orion O6 board device tree.
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b67d5b1fc45b..f9be52484008 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -241,6 +241,7 @@ CONFIG_PCIE_XILINX_DMA_PL=y
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCIE_XILINX_CPM=y
CONFIG_PCI_J721E_HOST=m
+CONFIG_PCI_SKY1_HOST=m
CONFIG_PCI_IMX6_HOST=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
@@ -676,6 +677,7 @@ CONFIG_PINCTRL_SDM660=y
CONFIG_PINCTRL_SDM670=y
CONFIG_PINCTRL_SDM845=y
CONFIG_PINCTRL_SDX75=y
+CONFIG_PINCTRL_SKY1=y
CONFIG_PINCTRL_SM4450=y
CONFIG_PINCTRL_SM6115=y
CONFIG_PINCTRL_SM6125=y
@@ -701,6 +703,7 @@ CONFIG_PINCTRL_SM8550_LPASS_LPI=m
CONFIG_PINCTRL_SM8650_LPASS_LPI=m
CONFIG_PINCTRL_SOPHGO_SG2000=y
CONFIG_GPIO_ALTERA=m
+CONFIG_GPIO_CADENCE=m
CONFIG_GPIO_DAVINCI=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_MB86S7X=y
--
2.50.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO
2026-03-27 11:46 [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO Peter Chen
@ 2026-03-30 7:56 ` Krzysztof Kozlowski
2026-05-21 15:23 ` Krzysztof Kozlowski
1 sibling, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-30 7:56 UTC (permalink / raw)
To: Peter Chen, arnd
Cc: krzysztof.kozlowski, geert+renesas, linux-kernel,
linux-arm-kernel, cix-kernel-upstream, Yunseong Kim
On 27/03/2026 12:46, Peter Chen wrote:
> Enable the CIX Sky1 pinctrl driver (PINCTRL_SKY1), CIX Sky1 PCIe host
> controller (PCI_SKY1_HOST), and Cadence GPIO controller (GPIO_CADENCE)
> for the Radxa Orion O6 board which uses the CIX Sky1 SoC.
>
> The pinctrl driver is a dependency for other on-SoC peripherals. The
> Cadence-based PCIe host controller enables use of PCIe peripherals on
> the board. The Cadence GPIO controller provides GPIO support for the
> SoC.
>
> Cc: Yunseong Kim <ysk@kzalloc•com>
> Signed-off-by: Peter Chen <peter.chen@cixtech•com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss•qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO
2026-03-27 11:46 [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO Peter Chen
2026-03-30 7:56 ` Krzysztof Kozlowski
@ 2026-05-21 15:23 ` Krzysztof Kozlowski
2026-05-21 15:46 ` Arnd Bergmann
1 sibling, 1 reply; 4+ messages in thread
From: Krzysztof Kozlowski @ 2026-05-21 15:23 UTC (permalink / raw)
To: Peter Chen, arnd
Cc: krzysztof.kozlowski, geert+renesas, linux-kernel,
linux-arm-kernel, cix-kernel-upstream, Yunseong Kim
On 27/03/2026 12:46, Peter Chen wrote:
> Enable the CIX Sky1 pinctrl driver (PINCTRL_SKY1), CIX Sky1 PCIe host
> controller (PCI_SKY1_HOST), and Cadence GPIO controller (GPIO_CADENCE)
> for the Radxa Orion O6 board which uses the CIX Sky1 SoC.
>
> The pinctrl driver is a dependency for other on-SoC peripherals. The
> Cadence-based PCIe host controller enables use of PCIe peripherals on
> the board. The Cadence GPIO controller provides GPIO support for the
> SoC.
>
> Cc: Yunseong Kim <ysk@kzalloc•com>
> Signed-off-by: Peter Chen <peter.chen@cixtech•com>
> ---
> Changes for v3:
> - Use specific driver names (CIX Sky1 pinctrl, CIX Sky1 PCIe host
> controller, Cadence GPIO) in subject and commit message instead of
> generic terms.
> - Remove external Debian bug reference; explain rationale directly.
> - Remove NVMe mention since only PCIe host controller is enabled.
>
> Changes for v2:
> - Delete CIX HDA configurations due to it is not used at current
> Orion O6 board device tree.
>
> arch/arm64/configs/defconfig | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index b67d5b1fc45b..f9be52484008 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -241,6 +241,7 @@ CONFIG_PCIE_XILINX_DMA_PL=y
> CONFIG_PCIE_XILINX_NWL=y
> CONFIG_PCIE_XILINX_CPM=y
> CONFIG_PCI_J721E_HOST=m
> +CONFIG_PCI_SKY1_HOST=m
This is not correctly placed and caused issues later - conflicts with my
cleanup patch.
Please fix it up before you send the patch to soc@.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO
2026-05-21 15:23 ` Krzysztof Kozlowski
@ 2026-05-21 15:46 ` Arnd Bergmann
0 siblings, 0 replies; 4+ messages in thread
From: Arnd Bergmann @ 2026-05-21 15:46 UTC (permalink / raw)
To: Krzysztof Kozlowski, Peter Chen
Cc: Krzysztof Kozlowski, Geert Uytterhoeven, linux-kernel,
linux-arm-kernel, cix-kernel-upstream, Yunseong Kim
On Thu, May 21, 2026, at 17:23, Krzysztof Kozlowski wrote:
> On 27/03/2026 12:46, Peter Chen wrote:
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index b67d5b1fc45b..f9be52484008 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -241,6 +241,7 @@ CONFIG_PCIE_XILINX_DMA_PL=y
>> CONFIG_PCIE_XILINX_NWL=y
>> CONFIG_PCIE_XILINX_CPM=y
>> CONFIG_PCI_J721E_HOST=m
>> +CONFIG_PCI_SKY1_HOST=m
>
> This is not correctly placed and caused issues later - conflicts with my
> cleanup patch.
>
> Please fix it up before you send the patch to soc@.
The problem was my merge, and I've fixed it up now, thanks
for pointing it out.
I don't think there was anything that Peter could have done
differently here, as the merge conflicts were to be
expected.
Arnd
^ permalink raw reply [flat|nested] 4+ messages in thread
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2026-03-27 11:46 [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO Peter Chen
2026-03-30 7:56 ` Krzysztof Kozlowski
2026-05-21 15:23 ` Krzysztof Kozlowski
2026-05-21 15:46 ` Arnd Bergmann
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