* [PATCH 0/3] ASoC: rockchip: Reorder clock enable sequence
@ 2026-05-22 10:03 phucduc.bui
2026-05-22 10:03 ` [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions phucduc.bui
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
From: bui duc phuc <phucduc.bui@gmail•com>
Hi all,
This series reorders the runtime resume clock enable
sequence in the Rockchip SPDIF and PDM drivers to enable
the bus clock before the functional controller clock.
It also updates the SPDIF DT binding clock descriptions to
match the actual clock usage in the driver.
Best Regards,
Phuc
bui duc phuc (3):
ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions
ASoC: rockchip: spdif: Reorder clock enable sequence
ASoC: rockchip: rockchip_pdm: Reorder clock enable sequence
.../devicetree/bindings/sound/rockchip-spdif.yaml | 2 +-
sound/soc/rockchip/rockchip_pdm.c | 10 +++++-----
sound/soc/rockchip/rockchip_spdif.c | 10 +++++-----
3 files changed, 11 insertions(+), 11 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions
2026-05-22 10:03 [PATCH 0/3] ASoC: rockchip: Reorder clock enable sequence phucduc.bui
@ 2026-05-22 10:03 ` phucduc.bui
2026-05-30 10:44 ` Krzysztof Kozlowski
2026-05-22 10:03 ` [PATCH 2/3] ASoC: rockchip: spdif: Reorder clock enable sequence phucduc.bui
2026-05-22 10:03 ` [PATCH 3/3] ASoC: rockchip: rockchip_pdm: " phucduc.bui
2 siblings, 1 reply; 6+ messages in thread
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
From: bui duc phuc <phucduc.bui@gmail•com>
The clock descriptions are currently swapped relative to the
clock names used by the driver.
Update the binding descriptions to match the actual clock
usage, where 'mclk' is the controller clock and 'hclk' is
the bus clock.
Signed-off-by: bui duc phuc <phucduc.bui@gmail•com>
---
Documentation/devicetree/bindings/sound/rockchip-spdif.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
index 502907dd28b3..b174d7498029 100644
--- a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
+++ b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
@@ -45,8 +45,8 @@ properties:
clocks:
items:
- - description: clock for SPDIF bus
- description: clock for SPDIF controller
+ - description: clock for SPDIF bus
clock-names:
items:
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] ASoC: rockchip: spdif: Reorder clock enable sequence
2026-05-22 10:03 [PATCH 0/3] ASoC: rockchip: Reorder clock enable sequence phucduc.bui
2026-05-22 10:03 ` [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions phucduc.bui
@ 2026-05-22 10:03 ` phucduc.bui
2026-05-22 10:03 ` [PATCH 3/3] ASoC: rockchip: rockchip_pdm: " phucduc.bui
2 siblings, 0 replies; 6+ messages in thread
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
From: bui duc phuc <phucduc.bui@gmail•com>
Enable the 'hclk' bus clock before the 'mclk' controller
clock during runtime resume.
The bus clock provides the register access interface and
should be enabled before the controller clock.
Signed-off-by: bui duc phuc <phucduc.bui@gmail•com>
---
sound/soc/rockchip/rockchip_spdif.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
index 581624f2682e..8de5b76cfe79 100644
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -76,16 +76,16 @@ static int rk_spdif_runtime_resume(struct device *dev)
struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
int ret;
- ret = clk_prepare_enable(spdif->mclk);
+ ret = clk_prepare_enable(spdif->hclk);
if (ret) {
- dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
+ dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
return ret;
}
- ret = clk_prepare_enable(spdif->hclk);
+ ret = clk_prepare_enable(spdif->mclk);
if (ret) {
- clk_disable_unprepare(spdif->mclk);
- dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
+ clk_disable_unprepare(spdif->hclk);
+ dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
return ret;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] ASoC: rockchip: rockchip_pdm: Reorder clock enable sequence
2026-05-22 10:03 [PATCH 0/3] ASoC: rockchip: Reorder clock enable sequence phucduc.bui
2026-05-22 10:03 ` [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions phucduc.bui
2026-05-22 10:03 ` [PATCH 2/3] ASoC: rockchip: spdif: Reorder clock enable sequence phucduc.bui
@ 2026-05-22 10:03 ` phucduc.bui
2 siblings, 0 replies; 6+ messages in thread
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
From: bui duc phuc <phucduc.bui@gmail•com>
Enable the 'hclk' bus clock before the 'clk' controller
clock during runtime resume.
The bus clock provides the register access interface and
should be enabled before the controller clock.
Signed-off-by: bui duc phuc <phucduc.bui@gmail•com>
---
sound/soc/rockchip/rockchip_pdm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c
index c69cdd6f2499..8f78f7bc1806 100644
--- a/sound/soc/rockchip/rockchip_pdm.c
+++ b/sound/soc/rockchip/rockchip_pdm.c
@@ -422,16 +422,16 @@ static int rockchip_pdm_runtime_resume(struct device *dev)
struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
int ret;
- ret = clk_prepare_enable(pdm->clk);
+ ret = clk_prepare_enable(pdm->hclk);
if (ret) {
- dev_err(pdm->dev, "clock enable failed %d\n", ret);
+ dev_err(pdm->dev, "hclock enable failed %d\n", ret);
return ret;
}
- ret = clk_prepare_enable(pdm->hclk);
+ ret = clk_prepare_enable(pdm->clk);
if (ret) {
- clk_disable_unprepare(pdm->clk);
- dev_err(pdm->dev, "hclock enable failed %d\n", ret);
+ clk_disable_unprepare(pdm->hclk);
+ dev_err(pdm->dev, "clock enable failed %d\n", ret);
return ret;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions
2026-05-22 10:03 ` [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions phucduc.bui
@ 2026-05-30 10:44 ` Krzysztof Kozlowski
2026-06-01 10:05 ` Bui Duc Phuc
0 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Kozlowski @ 2026-05-30 10:44 UTC (permalink / raw)
To: phucduc.bui
Cc: broonie, lgirdwood, perex, tiwai, heiko, linux-arm-kernel,
linux-kernel, linux-sound, linux-rockchip, robh, krzk+dt,
conor+dt, devicetree
On Fri, May 22, 2026 at 05:03:16PM +0700, phucduc.bui@gmail•com wrote:
> From: bui duc phuc <phucduc.bui@gmail•com>
>
> The clock descriptions are currently swapped relative to the
> clock names used by the driver.
Why would order of clock names in the driver matter here? I do not
understand that explanation.
>
> Update the binding descriptions to match the actual clock
> usage, where 'mclk' is the controller clock and 'hclk' is
> the bus clock.
Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
>
> Signed-off-by: bui duc phuc <phucduc.bui@gmail•com>
> ---
> Documentation/devicetree/bindings/sound/rockchip-spdif.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
> index 502907dd28b3..b174d7498029 100644
> --- a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
> +++ b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
> @@ -45,8 +45,8 @@ properties:
>
> clocks:
> items:
> - - description: clock for SPDIF bus
> - description: clock for SPDIF controller
> + - description: clock for SPDIF bus
So example is wrong?
What about all the users?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions
2026-05-30 10:44 ` Krzysztof Kozlowski
@ 2026-06-01 10:05 ` Bui Duc Phuc
0 siblings, 0 replies; 6+ messages in thread
From: Bui Duc Phuc @ 2026-06-01 10:05 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: broonie, lgirdwood, perex, tiwai, heiko, linux-arm-kernel,
linux-kernel, linux-sound, linux-rockchip, robh, krzk+dt,
conor+dt, devicetree
Hi Krzysztof,
Thank you for your review .
> So example is wrong?
>
> What about all the users?
I only updated the internal description text to match the existing clock-names.
The clock ordering (mclk followed by hclk) remains unchanged,
so external .dts files and the example section at the end of the
binding are unaffected.
> Please wrap commit message according to Linux coding style / submission
> process (neither too early nor over the limit):
> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
>
Thank you for the guidance. I will address this in v2.
> > The clock descriptions are currently swapped relative to the
> > clock names used by the driver.
>
> Why would order of clock names in the driver matter here? I do not
> understand that explanation.
>
I inferred that 'hclk' is the bus clock from the driver, which uses
devm_regmap_init_mmio_clk() with 'hclk',
and this matches the description found in several Rockchip datasheets.
However, I understand that the binding should be described
independently of the driver implementation.
Therefore, I'll drop this description in the next revision.
Best Regards,
Phuc
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-06-01 10:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2026-05-22 10:03 [PATCH 0/3] ASoC: rockchip: Reorder clock enable sequence phucduc.bui
2026-05-22 10:03 ` [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions phucduc.bui
2026-05-30 10:44 ` Krzysztof Kozlowski
2026-06-01 10:05 ` Bui Duc Phuc
2026-05-22 10:03 ` [PATCH 2/3] ASoC: rockchip: spdif: Reorder clock enable sequence phucduc.bui
2026-05-22 10:03 ` [PATCH 3/3] ASoC: rockchip: rockchip_pdm: " phucduc.bui
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