* [PATCH 0/3] soc: realtek: Add Realtek DHC I/O level detector support
@ 2026-06-04 11:18 Yu-Chun Lin
2026-06-04 11:18 ` [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector Yu-Chun Lin
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Yu-Chun Lin @ 2026-06-04 11:18 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, tychang
Cc: eleanor.lin, cy.huang, stanley_chang, james.tai, afaerber,
devicetree, linux-kernel, linux-arm-kernel, linux-realtek-soc
Hi all,
This patch series introduces support for the Realtek DHC I/O level detector.
The Realtek DHC I/O level detector is a hardware block responsible for
detecting the I/O signaling levels (1.8V or 3.3V) of various IP blocks
such as RGMII, SDIO, eMMC, CSI, SD, UART1, and AIO.
The driver reads the hardware registers to determine the current I/O voltage
levels. Based on these detection results, it dynamically selects and applies
the appropriate pinctrl states to ensure the correct pad configurations are
used for each interface.
Thanks,
Yu-Chun
Tzuyi Chang (2):
dt-bindings: soc: realtek: Add Realtek DHC I/O level detector
soc: realtek: Add driver for DHC I/O level detector
Yu-Chun Lin (1):
arm64: dts: realtek: Add I/O level detector
.../realtek/realtek,rtd1625-io-detect.yaml | 77 +++++++++
MAINTAINERS | 1 +
arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi | 108 +++++++++++++
arch/arm64/boot/dts/realtek/kent.dtsi | 28 ++++
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/realtek/Kconfig | 21 +++
drivers/soc/realtek/Makefile | 2 +
drivers/soc/realtek/rtd-io-detect.c | 152 ++++++++++++++++++
9 files changed, 391 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml
create mode 100644 arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi
create mode 100644 drivers/soc/realtek/Kconfig
create mode 100644 drivers/soc/realtek/Makefile
create mode 100644 drivers/soc/realtek/rtd-io-detect.c
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector
2026-06-04 11:18 [PATCH 0/3] soc: realtek: Add Realtek DHC I/O level detector support Yu-Chun Lin
@ 2026-06-04 11:18 ` Yu-Chun Lin
2026-06-04 12:49 ` Krzysztof Kozlowski
2026-06-04 11:18 ` [PATCH 2/3] soc: realtek: Add driver for " Yu-Chun Lin
2026-06-04 11:18 ` [PATCH 3/3] arm64: dts: realtek: Add " Yu-Chun Lin
2 siblings, 1 reply; 5+ messages in thread
From: Yu-Chun Lin @ 2026-06-04 11:18 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, tychang
Cc: eleanor.lin, cy.huang, stanley_chang, james.tai, afaerber,
devicetree, linux-kernel, linux-arm-kernel, linux-realtek-soc
From: Tzuyi Chang <tychang@realtek•com>
Add device tree binding documentation for the Realtek DHC I/O level
detector.
This hardware block is responsible for detecting the I/O signaling
levels (e.g., 1.8V or 3.3V) of various interfaces (RGMII, SDIO, eMMC,
etc.) and applying the corresponding pad configurations via pinctrl
states.
Signed-off-by: Tzuyi Chang <tychang@realtek•com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek•com>
---
.../realtek/realtek,rtd1625-io-detect.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml
diff --git a/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml
new file mode 100644
index 000000000000..badf27212dfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2026 Realtek Semiconductor Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/realtek/realtek,rtd1625-io-detect.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC I/O Level Detector
+
+maintainers:
+ - Tzuyi Chang <tychang@realtek•com>
+
+description: |
+ The Realtek DHC I/O Level Detector is a hardware block that detects I/O
+ signaling levels (such as 1.8V or 3.3V) to determine the correct pad
+ configurations for specific IP blocks.
+
+properties:
+ compatible:
+ const: realtek,rtd1625-io-detect
+
+ pinctrl-names:
+ items:
+ - const: rgmii_1v8
+ - const: rgmii_3v3
+ - const: sdio_1v8
+ - const: sdio_3v3
+ - const: csi_1v8
+ - const: csi_3v3
+ - const: sd_1v8
+ - const: sd_3v3
+ - const: uart1_1v8
+ - const: uart1_3v3
+ - const: aio_1v8
+ - const: aio_3v3
+ - const: emmc_1v8
+ - const: emmc_3v3
+
+ realtek,iso-pinctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Pinctrl phandle containing I/O detection registers.
+
+required:
+ - compatible
+ - pinctrl-names
+ - realtek,iso-pinctrl
+
+additionalProperties: false
+
+examples:
+ - |
+ io-detect {
+ compatible = "realtek,rtd1625-io-detect";
+ pinctrl-names = "rgmii_1v8", "rgmii_3v3",
+ "sdio_1v8", "sdio_3v3",
+ "csi_1v8", "csi_3v3",
+ "sd_1v8", "sd_3v3",
+ "uart1_1v8", "uart1_3v3",
+ "aio_1v8", "aio_3v3",
+ "emmc_1v8", "emmc_3v3";
+ pinctrl-0 = <&rgmii_vsel_1v8_pins>;
+ pinctrl-1 = <&rgmii_vsel_3v3_pins>;
+ pinctrl-2 = <&sdio_vsel_1v8_pins>;
+ pinctrl-3 = <&sdio_vsel_3v3_pins>;
+ pinctrl-4 = <&csi_vsel_1v8_pins>;
+ pinctrl-5 = <&csi_vsel_3v3_pins>;
+ pinctrl-6 = <&sd_vsel_1v8_pins>;
+ pinctrl-7 = <&sd_vsel_3v3_pins>;
+ pinctrl-8 = <&uart1_vsel_1v8_pins>;
+ pinctrl-9 = <&uart1_vsel_3v3_pins>;
+ pinctrl-10 = <&aio_vsel_1v8_pins>;
+ pinctrl-11 = <&aio_vsel_3v3_pins>;
+ pinctrl-12 = <&emmc_vsel_1v8_pins>;
+ pinctrl-13 = <&emmc_vsel_3v3_pins>;
+ realtek,iso-pinctrl = <&iso_pinctrl>;
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/3] soc: realtek: Add driver for DHC I/O level detector
2026-06-04 11:18 [PATCH 0/3] soc: realtek: Add Realtek DHC I/O level detector support Yu-Chun Lin
2026-06-04 11:18 ` [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector Yu-Chun Lin
@ 2026-06-04 11:18 ` Yu-Chun Lin
2026-06-04 11:18 ` [PATCH 3/3] arm64: dts: realtek: Add " Yu-Chun Lin
2 siblings, 0 replies; 5+ messages in thread
From: Yu-Chun Lin @ 2026-06-04 11:18 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, tychang
Cc: eleanor.lin, cy.huang, stanley_chang, james.tai, afaerber,
devicetree, linux-kernel, linux-arm-kernel, linux-realtek-soc
From: Tzuyi Chang <tychang@realtek•com>
Add driver support for the Realtek DHC I/O level detector.
The driver reads hardware registers to determine the current I/O voltage
levels (e.g., 1.8V or 3.3V) for specific IP blocks. Based on the
detection results, it selects and applies the appropriate pinctrl states
to ensure the correct pad configurations are used.
Signed-off-by: Tzuyi Chang <tychang@realtek•com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek•com>
---
MAINTAINERS | 1 +
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/realtek/Kconfig | 21 ++++
drivers/soc/realtek/Makefile | 2 +
drivers/soc/realtek/rtd-io-detect.c | 152 ++++++++++++++++++++++++++++
6 files changed, 178 insertions(+)
create mode 100644 drivers/soc/realtek/Kconfig
create mode 100644 drivers/soc/realtek/Makefile
create mode 100644 drivers/soc/realtek/rtd-io-detect.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ec290e38b44..6121eb4f904e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3379,6 +3379,7 @@ F: arch/arm/boot/dts/realtek/
F: arch/arm/mach-realtek/
F: arch/arm64/boot/dts/realtek/
F: drivers/pinctrl/realtek/
+F: drivers/soc/realtek/
ARM/RISC-V/RENESAS ARCHITECTURE
M: Geert Uytterhoeven <geert+renesas@glider•be>
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index a2d65adffb80..d63b9d4dc042 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -20,6 +20,7 @@ source "drivers/soc/microchip/Kconfig"
source "drivers/soc/nuvoton/Kconfig"
source "drivers/soc/pxa/Kconfig"
source "drivers/soc/qcom/Kconfig"
+source "drivers/soc/realtek/Kconfig"
source "drivers/soc/renesas/Kconfig"
source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/samsung/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index c9e689080ceb..8678b1001183 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -26,6 +26,7 @@ obj-y += nuvoton/
obj-y += pxa/
obj-y += amlogic/
obj-y += qcom/
+obj-y += realtek/
obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
diff --git a/drivers/soc/realtek/Kconfig b/drivers/soc/realtek/Kconfig
new file mode 100644
index 000000000000..4c5796c7f9f7
--- /dev/null
+++ b/drivers/soc/realtek/Kconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Realtek SoC drivers
+#
+menu "Realtek SoC drivers"
+ depends on ARCH_REALTEK || COMPILE_TEST
+
+config RTD_IO_LEVEL_DETECT
+ tristate "Realtek DHC I/O Level Detector"
+ depends on PINCTRL_RTD
+ select MFD_SYSCON
+ default ARCH_REALTEK
+ help
+ Enable support for the Realtek DHC I/O level detector.
+
+ This driver handles the auto-detection of I/O signaling levels
+ (such as 1.8V and 3.3V) and dynamically configures the pad states
+ for specific IP blocks.
+
+endmenu
+
diff --git a/drivers/soc/realtek/Makefile b/drivers/soc/realtek/Makefile
new file mode 100644
index 000000000000..c307e5bdb52d
--- /dev/null
+++ b/drivers/soc/realtek/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_RTD_IO_LEVEL_DETECT) += rtd-io-detect.o
diff --git a/drivers/soc/realtek/rtd-io-detect.c b/drivers/soc/realtek/rtd-io-detect.c
new file mode 100644
index 000000000000..84ef8ea23cb5
--- /dev/null
+++ b/drivers/soc/realtek/rtd-io-detect.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC I/O Level Detect driver
+ *
+ * Copyright (c) 2026 Realtek Semiconductor Corp.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+struct rtd_io_detect_desc_info {
+ const char *name;
+ const char *state_1v8;
+ const char *state_3v3;
+ unsigned int reg_offset;
+ unsigned int en_offset;
+ unsigned int status_offset;
+};
+
+struct rtd_io_detect_descs {
+ const struct rtd_io_detect_desc_info *info;
+ int num_descs;
+};
+
+struct rtd_io_detect_data {
+ const struct rtd_io_detect_descs *descs;
+ struct regmap *base;
+ struct device *dev;
+};
+
+#define RTD_IO_DETECT_DESC(_name, _reg_off, _en_off, _st_off) \
+ { \
+ .name = #_name, \
+ .state_1v8 = #_name "_1v8", \
+ .state_3v3 = #_name "_3v3", \
+ .reg_offset = _reg_off, \
+ .en_offset = _en_off, \
+ .status_offset = _st_off, \
+ }
+
+static const struct rtd_io_detect_desc_info rtd1625_io_detect_desc[] = {
+ RTD_IO_DETECT_DESC(rgmii, 0x1a0, 8, 1),
+ RTD_IO_DETECT_DESC(sd, 0x1a0, 9, 2),
+ RTD_IO_DETECT_DESC(csi, 0x1a0, 10, 3),
+ RTD_IO_DETECT_DESC(sdio, 0x1a0, 11, 4),
+ RTD_IO_DETECT_DESC(uart1, 0x1a0, 12, 5),
+ RTD_IO_DETECT_DESC(aio, 0x1a0, 13, 6),
+ RTD_IO_DETECT_DESC(emmc, 0x1a0, 14, 7),
+};
+
+static const struct rtd_io_detect_descs rtd1625_io_detect_descs = {
+ .info = rtd1625_io_detect_desc,
+ .num_descs = ARRAY_SIZE(rtd1625_io_detect_desc),
+};
+
+static void detect_io_set(struct pinctrl *pinctrl,
+ const struct rtd_io_detect_desc_info *desc,
+ struct rtd_io_detect_data *data)
+{
+ struct pinctrl_state *state_1v8;
+ struct pinctrl_state *state_3v3;
+ unsigned int val;
+ int ret;
+
+ state_1v8 = pinctrl_lookup_state(pinctrl, desc->state_1v8);
+ if (IS_ERR(state_1v8)) {
+ dev_err(data->dev, "Failed to lookup %s state: %ld\n",
+ desc->state_1v8, PTR_ERR(state_1v8));
+ return;
+ }
+
+ state_3v3 = pinctrl_lookup_state(pinctrl, desc->state_3v3);
+ if (IS_ERR(state_3v3)) {
+ dev_err(data->dev, "Failed to lookup %s state: %ld\n",
+ desc->state_3v3, PTR_ERR(state_3v3));
+ return;
+ }
+
+ regmap_update_bits(data->base, desc->reg_offset,
+ BIT(desc->en_offset), BIT(desc->en_offset));
+
+ regmap_read(data->base, desc->reg_offset, &val);
+
+ ret = pinctrl_select_state(pinctrl,
+ (val & BIT(desc->status_offset)) ? state_3v3 : state_1v8);
+ if (ret)
+ dev_err(data->dev, "Failed to select pinctrl state\n");
+}
+
+static int rtd_io_detect_probe(struct platform_device *pdev)
+{
+ struct rtd_io_detect_data *data;
+ struct device *dev = &pdev->dev;
+ struct device_node *pinctrl_np;
+ struct pinctrl *pinctrl;
+ int i;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ pinctrl_np = of_parse_phandle(dev->of_node, "realtek,iso-pinctrl", 0);
+ if (!pinctrl_np) {
+ dev_err(dev, "Failed to find ISO pinctrl node\n");
+ return -ENODEV;
+ }
+
+ data->base = device_node_to_regmap(pinctrl_np);
+ of_node_put(pinctrl_np);
+
+ if (IS_ERR(data->base))
+ return dev_err_probe(dev, PTR_ERR(data->base), "Failed to get regmap\n");
+
+ data->descs = device_get_match_data(dev);
+ if (!data->descs)
+ return -EINVAL;
+
+ pinctrl = devm_pinctrl_get(dev);
+ if (IS_ERR(pinctrl))
+ return dev_err_probe(dev, PTR_ERR(pinctrl), "Failed to get pinctrl\n");
+
+ data->dev = dev;
+
+ for (i = 0; i < data->descs->num_descs; i++)
+ detect_io_set(pinctrl, &data->descs->info[i], data);
+
+ return 0;
+}
+
+static const struct of_device_id rtd_io_detect_of_matches[] = {
+ { .compatible = "realtek,rtd1625-io-detect", .data = &rtd1625_io_detect_descs },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rtd_io_detect_of_matches);
+
+static struct platform_driver rtd_io_detect_driver = {
+ .driver = {
+ .name = "rtd_io_level_detect",
+ .of_match_table = rtd_io_detect_of_matches,
+ },
+ .probe = rtd_io_detect_probe,
+};
+module_platform_driver(rtd_io_detect_driver);
+
+MODULE_DESCRIPTION("Realtek DHC SoC I/O Level Detect driver");
+MODULE_LICENSE("GPL");
+
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] arm64: dts: realtek: Add I/O level detector
2026-06-04 11:18 [PATCH 0/3] soc: realtek: Add Realtek DHC I/O level detector support Yu-Chun Lin
2026-06-04 11:18 ` [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector Yu-Chun Lin
2026-06-04 11:18 ` [PATCH 2/3] soc: realtek: Add driver for " Yu-Chun Lin
@ 2026-06-04 11:18 ` Yu-Chun Lin
2 siblings, 0 replies; 5+ messages in thread
From: Yu-Chun Lin @ 2026-06-04 11:18 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, tychang
Cc: eleanor.lin, cy.huang, stanley_chang, james.tai, afaerber,
devicetree, linux-kernel, linux-arm-kernel, linux-realtek-soc
Add io-level-detector node with pinctrl configurations for 1.8V/3.3V
voltage selection on RGMII, SDIO, CSI, SD, UART1, AIO, and eMMC.
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek•com>
---
This patch depends on this pinctrl node patch [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/commit/?id=50d92732d10e
---
arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi | 108 ++++++++++++++++++
arch/arm64/boot/dts/realtek/kent.dtsi | 28 +++++
2 files changed, 136 insertions(+)
create mode 100644 arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi b/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi
new file mode 100644
index 000000000000..ec7e33034b96
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Copyright (c) 2022-2026 Realtek Semiconductor Corp.
+ */
+
+&iso_pinctrl {
+ aio_vsel_1v8_pins: aio-vsel-1v8-pins {
+ pins = "gpio_98", "gpio_99", "gpio_100", "gpio_101", "gpio_102", "gpio_103",
+ "gpio_104", "gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109",
+ "gpio_110", "gpio_111", "gpio_112";
+ power-source = <0>;
+ input-threshold-voltage-microvolt = <1800000>;
+ };
+
+ aio_vsel_3v3_pins: aio-vsel-3v3-pins {
+ pins = "gpio_98", "gpio_99", "gpio_100", "gpio_101", "gpio_102", "gpio_103",
+ "gpio_104", "gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109",
+ "gpio_110", "gpio_111", "gpio_112";
+ power-source = <1>;
+ input-threshold-voltage-microvolt = <3300000>;
+ };
+
+ csi_vsel_1v8_pins: csi-vsel-1v8-pins {
+ pins = "csi_vdsel";
+ function = "csi_1v8";
+ };
+
+ csi_vsel_3v3_pins: csi-vsel-3v3-pins {
+ pins = "csi_vdsel";
+ function = "csi_3v3";
+ };
+
+ rgmii_vsel_1v8_pins: rgmii-vsel-1v8-pins {
+ pins = "rgmii_vdsel";
+ function = "rgmii_1v8";
+ };
+
+ rgmii_vsel_3v3_pins: rgmii-vsel-3v3-pins {
+ pins = "rgmii_vdsel";
+ function = "rgmii_3v3";
+ };
+
+ sdio_vsel_1v8_pins: sdio-vsel-1v8-pins {
+ pins = "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", "gpio_50";
+ power-source = <0>;
+ };
+
+ sdio_vsel_3v3_pins: sdio-vsel-3v3-pins {
+ pins = "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", "gpio_50";
+ power-source = <1>;
+ };
+
+ uart1_vsel_1v8_pins: uart1-vsel-1v8-pins {
+ pins = "gpio_8", "gpio_9", "gpio_10", "gpio_11";
+ power-source = <0>;
+ input-threshold-voltage-microvolt = <1800000>;
+ };
+
+ uart1_vsel_3v3_pins: uart1-vsel-3v3-pins {
+ pins = "gpio_8", "gpio_9", "gpio_10", "gpio_11";
+ power-source = <1>;
+ input-threshold-voltage-microvolt = <3300000>;
+ };
+};
+
+&main2_pinctrl {
+ emmc_vsel_1v8_pins: emmc-vsel-1v8-pins {
+ pins = "emmc_rst_n",
+ "emmc_dd_sb",
+ "emmc_clk",
+ "emmc_cmd",
+ "emmc_data_0",
+ "emmc_data_1",
+ "emmc_data_2",
+ "emmc_data_3",
+ "emmc_data_4",
+ "emmc_data_5",
+ "emmc_data_6",
+ "emmc_data_7";
+ power-source = <0>;
+ };
+
+ emmc_vsel_3v3_pins: emmc-vsel-3v3-pins {
+ pins = "emmc_rst_n",
+ "emmc_dd_sb",
+ "emmc_clk",
+ "emmc_cmd",
+ "emmc_data_0",
+ "emmc_data_1",
+ "emmc_data_2",
+ "emmc_data_3",
+ "emmc_data_4",
+ "emmc_data_5",
+ "emmc_data_6",
+ "emmc_data_7";
+ power-source = <1>;
+ };
+
+ sd_vsel_1v8_pins: sd-vsel-1v8-pins {
+ pins = "gpio_40", "gpio_41", "hif_clk", "hif_data", "hif_en", "hif_rdy";
+ power-source = <0>;
+ };
+
+ sd_vsel_3v3_pins: sd-vsel-3v3-pins {
+ pins = "gpio_40", "gpio_41", "hif_clk", "hif_data", "hif_en", "hif_rdy";
+ power-source = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi
index 8d4293cd4c03..f18b975c3593 100644
--- a/arch/arm64/boot/dts/realtek/kent.dtsi
+++ b/arch/arm64/boot/dts/realtek/kent.dtsi
@@ -125,6 +125,32 @@ psci: psci {
method = "smc";
};
+ io_level_detector: io-level-detector {
+ compatible = "realtek,rtd1625-io-detect";
+ pinctrl-names = "rgmii_1v8", "rgmii_3v3",
+ "sdio_1v8", "sdio_3v3",
+ "csi_1v8", "csi_3v3",
+ "sd_1v8", "sd_3v3",
+ "uart1_1v8", "uart1_3v3",
+ "aio_1v8", "aio_3v3",
+ "emmc_1v8", "emmc_3v3";
+ pinctrl-0 = <&rgmii_vsel_1v8_pins>;
+ pinctrl-1 = <&rgmii_vsel_3v3_pins>;
+ pinctrl-2 = <&sdio_vsel_1v8_pins>;
+ pinctrl-3 = <&sdio_vsel_3v3_pins>;
+ pinctrl-4 = <&csi_vsel_1v8_pins>;
+ pinctrl-5 = <&csi_vsel_3v3_pins>;
+ pinctrl-6 = <&sd_vsel_1v8_pins>;
+ pinctrl-7 = <&sd_vsel_3v3_pins>;
+ pinctrl-8 = <&uart1_vsel_1v8_pins>;
+ pinctrl-9 = <&uart1_vsel_3v3_pins>;
+ pinctrl-10 = <&aio_vsel_1v8_pins>;
+ pinctrl-11 = <&aio_vsel_3v3_pins>;
+ pinctrl-12 = <&emmc_vsel_1v8_pins>;
+ pinctrl-13 = <&emmc_vsel_3v3_pins>;
+ realtek,iso-pinctrl = <&iso_pinctrl>;
+ };
+
soc@0 {
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
@@ -184,3 +210,5 @@ gic: interrupt-controller@ff100000 {
};
};
};
+
+#include "kent-pinctrl.dtsi"
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector
2026-06-04 11:18 ` [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector Yu-Chun Lin
@ 2026-06-04 12:49 ` Krzysztof Kozlowski
0 siblings, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2026-06-04 12:49 UTC (permalink / raw)
To: Yu-Chun Lin, robh, krzk+dt, conor+dt, tychang
Cc: cy.huang, stanley_chang, james.tai, afaerber, devicetree,
linux-kernel, linux-arm-kernel, linux-realtek-soc
On 04/06/2026 13:18, Yu-Chun Lin wrote:
> From: Tzuyi Chang <tychang@realtek•com>
>
> Add device tree binding documentation for the Realtek DHC I/O level
> detector.
>
> This hardware block is responsible for detecting the I/O signaling
> levels (e.g., 1.8V or 3.3V) of various interfaces (RGMII, SDIO, eMMC,
> etc.) and applying the corresponding pad configurations via pinctrl
> states.
>
> Signed-off-by: Tzuyi Chang <tychang@realtek•com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek•com>
> ---
> .../realtek/realtek,rtd1625-io-detect.yaml | 77 +++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml
> new file mode 100644
> index 000000000000..badf27212dfd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detect.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2026 Realtek Semiconductor Corporation
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/realtek/realtek,rtd1625-io-detect.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek DHC I/O Level Detector
> +
> +maintainers:
> + - Tzuyi Chang <tychang@realtek•com>
> +
> +description: |
Drop |
> + The Realtek DHC I/O Level Detector is a hardware block that detects I/O
> + signaling levels (such as 1.8V or 3.3V) to determine the correct pad
> + configurations for specific IP blocks.
> +
> +properties:
> + compatible:
> + const: realtek,rtd1625-io-detect
> +
No resources here, so does not look like a real device, but driver
instantiation.
> + pinctrl-names:
> + items:
> + - const: rgmii_1v8
> + - const: rgmii_3v3
> + - const: sdio_1v8
> + - const: sdio_3v3
> + - const: csi_1v8
> + - const: csi_3v3
> + - const: sd_1v8
> + - const: sd_3v3
> + - const: uart1_1v8
> + - const: uart1_3v3
> + - const: aio_1v8
> + - const: aio_3v3
> + - const: emmc_1v8
> + - const: emmc_3v3
> +
> + realtek,iso-pinctrl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Pinctrl phandle containing I/O detection registers.
MMIO registers are in 'reg' property.
> +
> +required:
> + - compatible
> + - pinctrl-names
> + - realtek,iso-pinctrl
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-06-04 12:49 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2026-06-04 11:18 [PATCH 0/3] soc: realtek: Add Realtek DHC I/O level detector support Yu-Chun Lin
2026-06-04 11:18 ` [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector Yu-Chun Lin
2026-06-04 12:49 ` Krzysztof Kozlowski
2026-06-04 11:18 ` [PATCH 2/3] soc: realtek: Add driver for " Yu-Chun Lin
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