From: swarren@wwwdotorg•org (Stephen Warren)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCHv4 2/7] driver/core: Populate IOMMU'able devices in order
Date: Wed, 13 Nov 2013 10:53:36 -0700 [thread overview]
Message-ID: <5283BCA0.40300@wwwdotorg.org> (raw)
In-Reply-To: <20131113173142.GF11928@mudshark.cambridge.arm.com>
On 11/13/2013 10:31 AM, Will Deacon wrote:
> On Wed, Nov 13, 2013 at 04:06:10PM +0000, Hiroshi Doyu wrote:
>> Will Deacon <will.deacon@arm•com> wrote @ Wed, 13 Nov 2013 15:38:04 +0100:
>>
>>> On Tue, Nov 12, 2013 at 11:34:20PM +0000, Stephen Warren wrote:
>>>> SMMU:
>>>> smmu: smmu at xxxxxx {
>>>> #smmu-cells = <1>;
>>>> }
>>>>
>>>> Affected device:
>>>> smmus = <&smmu 1>;
>>>> (perhaps with smmu-names too)
>>>>
>>>> That would allow the DT to represent basically arbitrary HW configurations.
>>>>
>>>> The implementation of this patch would then be almost as trivial; you'd
>>>> just need to walk the smmus property to find each phandle in turn, just
>>>> like any other phandle+specifier property, and validate that the SMMU
>>>> driver was already probe()d for each.
>>>
>>> There are a few problems with that:
>>>
>>> 1.) It assumes all devices sharing an SMMU have the same number of
>>> "smmu cells"
>>
>> This can be solved with introducing the fixed size of bitmap. The size
>> of bitmap can be fixed even per SoC. In tegra we used 64(2 cells)
>> which I expect at most.
>
> That really doesn't sound like a good idea where you have bridges (like a
> PCIe host controller) which could have a significant chunk of StreamID
> space. You'd also need to pad everything out with some dummy IDs for parsing
> purposes. Yuck!
Can't you solve this by having the SMMU include a stream ID mapping
table. In the case of stream IDs having a large "address" space, then
just define the mapping table syntax to allow easy specification of
ranges using start/length, start/end, or value/mask pairs. Similar to
ranges or PCI's interrupt-map{,-mask}.
next prev parent reply other threads:[~2013-11-13 17:53 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-11 8:31 [PATCHv4 0/7] Unifying SMMU driver among Tegra SoCs Hiroshi Doyu
2013-11-11 8:31 ` [PATCHv4 1/7] ARM: tegra: Create a DT header defining SWGROUP ID Hiroshi Doyu
2013-11-12 22:48 ` Stephen Warren
2013-11-15 10:29 ` Hiroshi Doyu
2013-11-15 16:44 ` Stephen Warren
2013-11-11 8:31 ` [PATCHv4 2/7] driver/core: Populate IOMMU'able devices in order Hiroshi Doyu
2013-11-11 11:39 ` Will Deacon
2013-11-12 23:30 ` Stephen Warren
2013-11-12 23:34 ` Stephen Warren
2013-11-13 7:23 ` Hiroshi Doyu
2013-11-13 17:49 ` Stephen Warren
2013-11-13 14:38 ` Will Deacon
2013-11-13 16:06 ` Hiroshi Doyu
2013-11-13 17:31 ` Will Deacon
2013-11-13 17:53 ` Stephen Warren [this message]
2013-11-14 16:16 ` Will Deacon
2013-11-13 17:45 ` Stephen Warren
2013-11-11 8:31 ` [PATCHv4 3/7] iommu/tegra: smmu: Register IOMMU'able devices dynamically Hiroshi Doyu
2013-11-12 23:53 ` Stephen Warren
2013-11-12 23:58 ` Stephen Warren
2013-11-11 8:31 ` [PATCHv4 4/7] iommu/tegra: smmu: Calculate ASID register offset by ID Hiroshi Doyu
2013-11-13 0:02 ` Stephen Warren
2013-11-11 8:31 ` [PATCHv4 5/7] iommu/tegra: smmu: Support "mmu-masters" binding Hiroshi Doyu
2013-11-11 11:35 ` Will Deacon
2013-11-11 12:03 ` Hiroshi Doyu
2013-11-13 0:17 ` Stephen Warren
2013-11-13 7:45 ` Hiroshi Doyu
2013-11-13 17:58 ` Stephen Warren
2013-11-14 6:41 ` Hiroshi Doyu
2013-11-14 16:59 ` Stephen Warren
2013-11-13 11:15 ` Kumar Gala
2013-11-11 8:31 ` [PATCHv4 6/7] iommu/tegra: smmu: Rename hwgrp -> swgroups Hiroshi Doyu
2013-11-11 8:31 ` [PATCHv4 7/7] iommu/tegra: smmu: Allow duplicate ASID wirte Hiroshi Doyu
2013-11-13 0:27 ` Stephen Warren
2013-11-12 22:40 ` [PATCHv4 0/7] Unifying SMMU driver among Tegra SoCs Stephen Warren
2013-11-13 6:04 ` Hiroshi Doyu
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