From: gregory.clement@free-electrons•com (Gregory CLEMENT)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v4 12/13] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC
Date: Wed, 19 Feb 2014 18:19:51 +0100 [thread overview]
Message-ID: <5304E7B7.3040206@free-electrons.com> (raw)
In-Reply-To: <20140219175145.4b4fcba5@skate>
On 19/02/2014 17:51, Thomas Petazzoni wrote:
> Dear Gregory CLEMENT,
>
> On Thu, 13 Feb 2014 18:33:35 +0100, Gregory CLEMENT wrote:
>
>> +config ARM_ARMADA_370_XP_CPUIDLE
>> + bool "CPU Idle Driver for Armada 370/XP family processors"
>
> Sorry to bring the naming issue, but it looks like the Armada 38x has a
> PMSU that looks almost identical to the Armada XP PMSU, except that it
> doesn't have the L2 fabric registers (probably because Armada 38x uses
> the PL310 and not the Marvell L2 cache).
>
> Therefore, should this cpuidle driver be named Armada 370/XP, or
> ARMADA_MVEBU for example?
Well most of the code is related to the coherency and the L2 cache, so
a different L2 cache is a significant difference. The CPU are also different
for example the PJ4B can use LDREX/STREX without MMU whereas the Cortex A9
can't.
>
>> +noinline static int armada_370_xp_cpu_suspend(unsigned long deepidle)
>
>
>
>> +{
>> + armada_370_xp_pmsu_idle_prepare(deepidle);
>> +
>> + v7_exit_coherency_flush(all);
>> +
>> + ll_clear_cpu_coherent();
>> +
>> + dsb();
>> +
>> + wfi();
>> +
>> + ll_set_cpu_coherent();
>> +
>> + asm volatile(
>> + "mrc p15, 0, %0, c1, c0, 0 \n\t"
>> + "tst %0, #(1 << 2) \n\t"
>> + "orreq r0, %0, #(1 << 2) \n\t"
>> + "mcreq p15, 0, %0, c1, c0, 0 \n\t"
>> + "isb "
>> + : : "r" (0));
>
> I believe a little comment on top of this assembly block would be good
> to have, to at least give a quick idea on what's going on.
I am on it, I had the same remark from Lorenzo Pieralisi.
>
> Also, I'm a bit unsure about your choice of mixing C and assembly here.
> This function is already calling ll_clear_cpu_coherent() and
> ll_set_cpu_coherent() that are assembly functions implement in
> coherency_ll.S. Shouldn't we do the same for this final bit of assembly?
I made several tries when I converted most of the code in C, so I am not
sure but I think that using a C function didn't work here. But as Lorenzo
pointed they were mistakes in this code, so once I will have fixed them, I
will try again.
Thanks,
Gregory
>
> Thomas
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2014-02-19 17:19 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-13 17:33 [PATCH v4 00/13] CPU idle for Armada XP Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 01/13] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B Gregory CLEMENT
2014-02-14 16:06 ` Lorenzo Pieralisi
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 02/13] ARM: mvebu: remove the address parameter for ll_set_cpu_coherent Gregory CLEMENT
2014-02-19 16:06 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 03/13] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU Gregory CLEMENT
2014-02-19 16:09 ` Thomas Petazzoni
2014-02-19 16:17 ` Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 04/13] ARM: mvebu: Remove the unused argument of set_cpu_coherent() Gregory CLEMENT
2014-02-19 16:27 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 05/13] ARM: mvebu: Low level function to disable HW coherency support Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 06/13] ARM: mvebu: Add a new set of registers for pmsu Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 07/13] ARM: dts: mvebu: Add a new set of registers to the PMSU node Gregory CLEMENT
2014-02-17 2:57 ` Jason Cooper
2014-02-19 16:00 ` Thomas Petazzoni
2014-02-19 17:49 ` Gregory CLEMENT
2014-02-19 18:21 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 08/13] ARM: mvebu: Allow to power down L2 cache controller in idle mode Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 09/13] ARM: mvebu: Add the PMSU related part of the cpu idle functions Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 10/13] ARM: mvebu: Set the start address of a CPU in a separate function Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 11/13] ARM: mvebu: Register notifier callback for the cpuidle transition Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 12/13] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC Gregory CLEMENT
2014-02-14 17:00 ` Lorenzo Pieralisi
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-17 8:49 ` Daniel Lezcano
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-19 16:51 ` Thomas Petazzoni
2014-02-19 17:19 ` Gregory CLEMENT [this message]
2014-02-19 18:32 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 13/13] ARM: mvebu: register the cpuidle driver for the Armada XP SoCs Gregory CLEMENT
2014-02-19 16:46 ` Thomas Petazzoni
2014-02-19 16:52 ` Gregory CLEMENT
2014-02-19 17:01 ` Thomas Petazzoni
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