From: gregory.clement@free-electrons•com (Gregory CLEMENT)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v4 01/13] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B
Date: Tue, 25 Mar 2014 23:57:22 +0100 [thread overview]
Message-ID: <533209D2.5070303@free-electrons.com> (raw)
In-Reply-To: <20140214160636.GC25043@e102568-lin.cambridge.arm.com>
On 14/02/2014 17:06, Lorenzo Pieralisi wrote:
> Hi Gregory,
>
> On Thu, Feb 13, 2014 at 05:33:24PM +0000, Gregory CLEMENT wrote:
>> PJ4B needs extra instructions for suspend and resume, so instead of
>> using the armv7 version, this commit introduces specific versions for
>> PJ4B.
>>
>> Cc: Russell King <linux@arm•linux.org.uk>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons•com>
>> ---
>> arch/arm/mm/proc-v7.S | 64 ++++++++++++++++++++++++++++++++++++++++++++++++---
>> 1 file changed, 61 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
>> index bd1781979a39..11117423a9b4 100644
>> --- a/arch/arm/mm/proc-v7.S
>> +++ b/arch/arm/mm/proc-v7.S
>> @@ -169,9 +169,67 @@ ENDPROC(cpu_pj4b_do_idle)
>> globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
>> #endif
>> globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
>> - globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
>> - globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
>> - globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
>> +#ifdef CONFIG_ARM_CPU_SUSPEND
>> +ENTRY(cpu_pj4b_do_suspend)
>> + stmfd sp!, {r4 - r10, lr}
>> + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
>> + mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
>> + stmia r0!, {r4 - r5}
>> + mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
>> + mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
>> + mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
>> + mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
>> + mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
>> + stmia r0!, {r6 - r10}
>> + mrc p15, 0, r6, c3, c0, 0 @ Domain ID
>> + mrc p15, 0, r7, c2, c0, 1 @ TTB 1
>> + mrc p15, 0, r11, c2, c0, 2 @ TTB control register
>> + mrc p15, 0, r8, c1, c0, 0 @ Control register
>> + mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
>> + mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
>> + stmia r0, {r6 - r11}
>> + ldmfd sp!, {r4 - r10, pc}
>> +ENDPROC(cpu_pj4b_do_suspend)
>> +
>> +ENTRY(cpu_pj4b_do_resume)
>> + mov ip, #0
>> + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
>> + mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
>> + ldmia r0!, {r4 - r5}
>> + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
>> + mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
>> + ldmia r0!, {r6 - r10}
>> + mcr p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
>> + mcr p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
>> + mcr p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
>> + mcr p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
>> + mcr p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
>> + ldmia r0, {r6 - r11}
>> + mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
>> + mcr p15, 0, r6, c3, c0, 0 @ Domain ID
>> +#ifndef CONFIG_ARM_LPAE
>> + ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
>> + ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
>> +#endif
>> + mcr p15, 0, r1, c2, c0, 0 @ TTB 0
>> + mcr p15, 0, r7, c2, c0, 1 @ TTB 1
>> + mcr p15, 0, r11, c2, c0, 2 @ TTB control register
>> + ldr r4, =PRRR @ PRRR
>> + ldr r5, =NMRR @ NMRR
>> + mcr p15, 0, r4, c10, c2, 0 @ write PRRR
>> + mcr p15, 0, r5, c10, c2, 1 @ write NMRR
>> + mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
>> + teq r4, r9 @ Is it already set?
>> + mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
>> + mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
>> + isb
>> + dsb
>> + mov r0, r8 @ control register
>> + b cpu_resume_mmu
>> +ENDPROC(cpu_pj4b_do_resume)
>> +#endif
>> +.globl cpu_pj4b_suspend_size
>> +.equ cpu_pj4b_suspend_size, 4 * 13
>>
>> #endif
>
> A couple of questions:
>
> 1) Do the extra registers ever change after coldboot ?
> 2) Do you need to restore them before turning the MMU and caches on ?
yes we need it.
> 3) Most of the code is copy'n'paste from v7, is not it possible to reuse
> that code by doing processor specific save/restore and then jump to
> the v7 functions ?
Yes it was possible and I have done it in the 5th version I have just sent.
>
> Thanks,
> Lorenzo
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2014-03-25 22:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-13 17:33 [PATCH v4 00/13] CPU idle for Armada XP Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 01/13] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B Gregory CLEMENT
2014-02-14 16:06 ` Lorenzo Pieralisi
2014-03-25 22:57 ` Gregory CLEMENT [this message]
2014-02-13 17:33 ` [PATCH v4 02/13] ARM: mvebu: remove the address parameter for ll_set_cpu_coherent Gregory CLEMENT
2014-02-19 16:06 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 03/13] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU Gregory CLEMENT
2014-02-19 16:09 ` Thomas Petazzoni
2014-02-19 16:17 ` Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 04/13] ARM: mvebu: Remove the unused argument of set_cpu_coherent() Gregory CLEMENT
2014-02-19 16:27 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 05/13] ARM: mvebu: Low level function to disable HW coherency support Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 06/13] ARM: mvebu: Add a new set of registers for pmsu Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 07/13] ARM: dts: mvebu: Add a new set of registers to the PMSU node Gregory CLEMENT
2014-02-17 2:57 ` Jason Cooper
2014-02-19 16:00 ` Thomas Petazzoni
2014-02-19 17:49 ` Gregory CLEMENT
2014-02-19 18:21 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 08/13] ARM: mvebu: Allow to power down L2 cache controller in idle mode Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 09/13] ARM: mvebu: Add the PMSU related part of the cpu idle functions Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 10/13] ARM: mvebu: Set the start address of a CPU in a separate function Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 11/13] ARM: mvebu: Register notifier callback for the cpuidle transition Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 12/13] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC Gregory CLEMENT
2014-02-14 17:00 ` Lorenzo Pieralisi
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-17 8:49 ` Daniel Lezcano
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-19 16:51 ` Thomas Petazzoni
2014-02-19 17:19 ` Gregory CLEMENT
2014-02-19 18:32 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 13/13] ARM: mvebu: register the cpuidle driver for the Armada XP SoCs Gregory CLEMENT
2014-02-19 16:46 ` Thomas Petazzoni
2014-02-19 16:52 ` Gregory CLEMENT
2014-02-19 17:01 ` Thomas Petazzoni
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