From: kishon@ti•com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 4/4] phy: rockchip-emmc: reindent the register definitions
Date: Mon, 20 Jun 2016 18:42:08 +0530 [thread overview]
Message-ID: <5767EBA8.1060603@ti.com> (raw)
In-Reply-To: <1463092986-61777-4-git-send-email-briannorris@chromium.org>
On Friday 13 May 2016 04:13 AM, Brian Norris wrote:
> Some of the spacing was wrong (spaces instead of tabs), and due to
> longer entries added later, the columns weren't aligned. Let's get
> everything consistent.
>
> Signed-off-by: Brian Norris <briannorris@chromium•org>
Acked-by: Kishon Vijay Abraham I <kishon@ti•com>
> ---
> drivers/phy/phy-rockchip-emmc.c | 76 ++++++++++++++++++++---------------------
> 1 file changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
> index f94d3a6587ed..c27ca2b39dfe 100644
> --- a/drivers/phy/phy-rockchip-emmc.c
> +++ b/drivers/phy/phy-rockchip-emmc.c
> @@ -31,44 +31,44 @@
> ((val) << (shift) | (mask) << ((shift) + 16))
>
> /* Register definition */
> -#define GRF_EMMCPHY_CON0 0x0
> -#define GRF_EMMCPHY_CON1 0x4
> -#define GRF_EMMCPHY_CON2 0x8
> -#define GRF_EMMCPHY_CON3 0xc
> -#define GRF_EMMCPHY_CON4 0x10
> -#define GRF_EMMCPHY_CON5 0x14
> -#define GRF_EMMCPHY_CON6 0x18
> -#define GRF_EMMCPHY_STATUS 0x20
> -
> -#define PHYCTRL_PDB_MASK 0x1
> -#define PHYCTRL_PDB_SHIFT 0x0
> -#define PHYCTRL_PDB_PWR_ON 0x1
> -#define PHYCTRL_PDB_PWR_OFF 0x0
> -#define PHYCTRL_ENDLL_MASK 0x1
> -#define PHYCTRL_ENDLL_SHIFT 0x1
> -#define PHYCTRL_ENDLL_ENABLE 0x1
> -#define PHYCTRL_ENDLL_DISABLE 0x0
> -#define PHYCTRL_CALDONE_MASK 0x1
> -#define PHYCTRL_CALDONE_SHIFT 0x6
> -#define PHYCTRL_CALDONE_DONE 0x1
> -#define PHYCTRL_CALDONE_GOING 0x0
> -#define PHYCTRL_DLLRDY_MASK 0x1
> -#define PHYCTRL_DLLRDY_SHIFT 0x5
> -#define PHYCTRL_DLLRDY_DONE 0x1
> -#define PHYCTRL_DLLRDY_GOING 0x0
> -#define PHYCTRL_FREQSEL_200M 0x0
> -#define PHYCTRL_FREQSEL_50M 0x1
> -#define PHYCTRL_FREQSEL_100M 0x2
> -#define PHYCTRL_FREQSEL_150M 0x3
> -#define PHYCTRL_FREQSEL_MASK 0x3
> -#define PHYCTRL_FREQSEL_SHIFT 0xc
> -#define PHYCTRL_DR_MASK 0x7
> -#define PHYCTRL_DR_SHIFT 0x4
> -#define PHYCTRL_DR_50OHM 0x0
> -#define PHYCTRL_DR_33OHM 0x1
> -#define PHYCTRL_DR_66OHM 0x2
> -#define PHYCTRL_DR_100OHM 0x3
> -#define PHYCTRL_DR_40OHM 0x4
> +#define GRF_EMMCPHY_CON0 0x0
> +#define GRF_EMMCPHY_CON1 0x4
> +#define GRF_EMMCPHY_CON2 0x8
> +#define GRF_EMMCPHY_CON3 0xc
> +#define GRF_EMMCPHY_CON4 0x10
> +#define GRF_EMMCPHY_CON5 0x14
> +#define GRF_EMMCPHY_CON6 0x18
> +#define GRF_EMMCPHY_STATUS 0x20
> +
> +#define PHYCTRL_PDB_MASK 0x1
> +#define PHYCTRL_PDB_SHIFT 0x0
> +#define PHYCTRL_PDB_PWR_ON 0x1
> +#define PHYCTRL_PDB_PWR_OFF 0x0
> +#define PHYCTRL_ENDLL_MASK 0x1
> +#define PHYCTRL_ENDLL_SHIFT 0x1
> +#define PHYCTRL_ENDLL_ENABLE 0x1
> +#define PHYCTRL_ENDLL_DISABLE 0x0
> +#define PHYCTRL_CALDONE_MASK 0x1
> +#define PHYCTRL_CALDONE_SHIFT 0x6
> +#define PHYCTRL_CALDONE_DONE 0x1
> +#define PHYCTRL_CALDONE_GOING 0x0
> +#define PHYCTRL_DLLRDY_MASK 0x1
> +#define PHYCTRL_DLLRDY_SHIFT 0x5
> +#define PHYCTRL_DLLRDY_DONE 0x1
> +#define PHYCTRL_DLLRDY_GOING 0x0
> +#define PHYCTRL_FREQSEL_200M 0x0
> +#define PHYCTRL_FREQSEL_50M 0x1
> +#define PHYCTRL_FREQSEL_100M 0x2
> +#define PHYCTRL_FREQSEL_150M 0x3
> +#define PHYCTRL_FREQSEL_MASK 0x3
> +#define PHYCTRL_FREQSEL_SHIFT 0xc
> +#define PHYCTRL_DR_MASK 0x7
> +#define PHYCTRL_DR_SHIFT 0x4
> +#define PHYCTRL_DR_50OHM 0x0
> +#define PHYCTRL_DR_33OHM 0x1
> +#define PHYCTRL_DR_66OHM 0x2
> +#define PHYCTRL_DR_100OHM 0x3
> +#define PHYCTRL_DR_40OHM 0x4
> #define PHYCTRL_OTAPDLYENA 0x1
> #define PHYCTRL_OTAPDLYENA_MASK 0x1
> #define PHYCTRL_OTAPDLYENA_SHIFT 0xb
>
next prev parent reply other threads:[~2016-06-20 13:12 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-12 22:43 [PATCH 1/4] phy: rockchip-emmc: give DLL some extra time to be ready Brian Norris
2016-05-12 22:43 ` [PATCH 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Brian Norris
2016-05-13 1:02 ` Shawn Lin
2016-05-13 18:46 ` Doug Anderson
2016-05-13 21:04 ` Brian Norris
2016-05-24 4:51 ` Doug Anderson
2016-05-13 21:09 ` [PATCH v2 " Brian Norris
2016-05-13 22:04 ` Doug Anderson
2016-06-16 23:36 ` Heiko Stuebner
2016-06-20 13:11 ` [PATCH " Kishon Vijay Abraham I
2016-05-12 22:43 ` [PATCH 3/4] phy: rockchip-emmc: configure default output tap delay Brian Norris
2016-05-13 22:25 ` Doug Anderson
2016-05-16 4:15 ` Shawn Lin
2016-05-16 15:12 ` Doug Anderson
2016-06-16 23:36 ` Heiko Stuebner
2016-06-20 13:11 ` Kishon Vijay Abraham I
2016-05-12 22:43 ` [PATCH 4/4] phy: rockchip-emmc: reindent the register definitions Brian Norris
2016-05-13 22:26 ` Doug Anderson
2016-06-16 23:37 ` Heiko Stuebner
2016-06-20 13:12 ` Kishon Vijay Abraham I [this message]
2016-05-13 22:01 ` [PATCH 1/4] phy: rockchip-emmc: give DLL some extra time to be ready Doug Anderson
2016-06-16 23:35 ` Heiko Stuebner
2016-06-20 13:11 ` Kishon Vijay Abraham I
2016-06-20 16:19 ` Brian Norris
2016-06-20 16:25 ` Doug Anderson
2016-06-20 16:50 ` Brian Norris
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