From: Gerd Bayer <gbayer@linux•ibm.com>
To: 18255117159@163•com, bhelgaas@google•com, helgaas@kernel•org
Cc: gbayer@linux•ibm.com, agordeev@linux•ibm.com,
borntraeger@linux•ibm.com, ilpo.jarvinen@linux•intel.com,
jingoohan1@gmail•com, kwilczynski@kernel•org,
linux-kernel@vger•kernel.org, linux-s390@vger•kernel.org,
linux-next@vger•kernel.org, linux-pci@vger•kernel.org,
lpieralisi@kernel•org, mani@kernel•org, robh@kernel•org,
schnelle@linux•ibm.com
Subject: [PATCH] PCI: Fix endianness issues in pci_bus_read_config()
Date: Thu, 31 Jul 2025 19:38:58 +0200 [thread overview]
Message-ID: <20250731173858.1173442-1-gbayer@linux.ibm.com> (raw)
In-Reply-To: <4e10bea3aa91ee721bb40e9388e8f72f930908fe.camel@linux.ibm.com>
Simple pointer-casts to map byte and word reads from PCI config space
into dwords (i.e. u32) produce unintended results on big-endian systems.
Add the necessary adjustments under compile-time switch
CONFIG_CPU_BIG_ENDIAN.
pci_bus_read_config() was just introduced with
https://lore.kernel.org/all/20250716161203.83823-2-18255117159@163.com/
Signed-off-by: Gerd Bayer <gbayer@linux•ibm.com>
---
Hi Hans, hi Bjorn,
Sorry to spill this endianness aware code into drivers/pci, feel free to
suggest a cleaner approach. This has fixed the issues seen on s390 systems
Otherwise it is just compile-tested for x86 and arm64.
Since this is still sitting in the a pull-request for upstream, I'm not sure if this
warrants a Fixes: tag.
Thanks,
Gerd
---
drivers/pci/access.c | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index ba66f55d2524..77a73b772a28 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -89,15 +89,24 @@ int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size,
u32 *val)
{
struct pci_bus *bus = priv;
+ int rc;
- if (size == 1)
- return pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
- else if (size == 2)
- return pci_bus_read_config_word(bus, devfn, where, (u16 *)val);
- else if (size == 4)
- return pci_bus_read_config_dword(bus, devfn, where, val);
- else
- return PCIBIOS_BAD_REGISTER_NUMBER;
+ if (size == 1) {
+ rc = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
+#if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+ *val = ((*val >> 24) & 0xff);
+#endif
+ } else if (size == 2) {
+ rc = pci_bus_read_config_word(bus, devfn, where, (u16 *)val);
+#if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+ *val = ((*val >> 16) & 0xffff);
+#endif
+ } else if (size == 4) {
+ rc = pci_bus_read_config_dword(bus, devfn, where, val);
+ } else {
+ rc = PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+ return rc;
}
int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
--
2.48.1
next prev parent reply other threads:[~2025-07-31 17:39 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250716231121.GA2564572@bhelgaas>
2025-07-31 7:32 ` [REGRESSION] next/master: suspect endianness issue in common PCI capability search macro Gerd Bayer
2025-07-31 17:38 ` Gerd Bayer [this message]
2025-07-31 18:39 ` [PATCH] PCI: Fix endianness issues in pci_bus_read_config() Bjorn Helgaas
2025-07-31 19:01 ` Arnd Bergmann
2025-08-01 8:18 ` Manivannan Sadhasivam
2025-08-01 9:25 ` Hans Zhang
2025-08-01 9:47 ` Manivannan Sadhasivam
2025-08-01 10:06 ` Hans Zhang
2025-08-01 10:54 ` Manivannan Sadhasivam
2025-08-01 11:30 ` Gerd Bayer
2025-08-01 16:54 ` Hans Zhang
2025-08-01 18:08 ` Keith Busch
2025-08-02 15:23 ` Hans Zhang
2025-08-02 15:40 ` Arnd Bergmann
2025-08-04 3:06 ` Hans Zhang
2025-08-04 8:03 ` Arnd Bergmann
2025-08-04 8:25 ` Hans Zhang
2025-08-04 10:09 ` Gerd Bayer
2025-08-12 14:44 ` Hans Zhang
2025-08-13 7:47 ` Niklas Schnelle
2025-08-13 7:50 ` Hans Zhang
2025-08-04 14:33 ` Bjorn Helgaas
2025-08-04 15:04 ` Hans Zhang
2025-08-01 16:47 ` Hans Zhang
2025-07-31 18:53 ` Lukas Wunner
2025-08-01 7:52 ` Geert Uytterhoeven
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