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From: marc_gonzalez@sigmadesigns•com (Marc Gonzalez)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v3] arm-soc: Add support for Sigma Designs Tango4
Date: Mon, 19 Oct 2015 13:09:22 +0200	[thread overview]
Message-ID: <5624CF62.6020001@sigmadesigns.com> (raw)
In-Reply-To: <CAL_JsqKa4trfpLY_DPsjBrfH-7SSUQMACYVW7DNN1=Pv3B4FrA@mail.gmail.com>

On 13/10/2015 19:55, Rob Herring wrote:
> Marc Gonzalez wrote:
>> On 09/10/2015 16:08, Rob Herring wrote:
>>
>>> No cpus node?
>>
>> Is this used to document the CPU?
>> I didn't see any code making use of that information.
> 
> The SMP code uses it: arch/arm/kernel/devtree.c

Now I see arm_dt_init_cpu_maps()

<confused> I thought DT was used to specify things that cannot be
dynamically discovered? Isn't it possible for the OS to discover at
run-time how many cores and/or CPUs are present?

On a related topic, I have a DTS for my board, which includes the
DTS for the architecture. However, there are single-core SoCs and
dual-core SoCs. Where is the cpus node supposed to appear?

Or should I specify in the architecture DTS the maximum number
of cores, as in

    cpus {
        #address-cells = <1>;
        #size-cells = <0>;
        cpu at 0 {
            compatible = "arm,cortex-a9";
            reg = <0>;
        };
        cpu at 1 {
            compatible = "arm,cortex-a9";
            reg = <1>;
        };
    };


>>> No pl310? A9 performance mon?

Found "arm,cortex-a9-pmu" in arch/arm/kernel/perf_event_v7.c
Are the PMU registers available from non-secure mode, or is TrustZone
going to get in the way?


About the cache controller, I was confused by this comment:
	/*
	 * Always enable non-secure access to the lockdown registers -
	 * we write to them as part of the L2C enable sequence so they
	 * need to be accessible.
	 */
	l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN;

I see no lock() function, only unlock().

But the unlock function merely writes 0 to the relevant registers,
and 0 is the value at reset for those registers. Since nothing ever
sets the registers to non-zero, why is the unlock needed at all?


Regards.

  reply	other threads:[~2015-10-19 11:09 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-02 16:02 [PATCH] arm-soc: Add Sigma Designs Tango4 port Mason
2015-10-02 16:10 ` Måns Rullgård
2015-10-02 16:33   ` Mason
2015-10-02 16:55     ` Måns Rullgård
2015-10-02 18:00       ` Mason
2015-10-02 17:13     ` Russell King - ARM Linux
2015-10-02 18:09       ` Mason
2015-10-02 18:53         ` Russell King - ARM Linux
2015-10-02 19:25           ` Mason
2015-10-02 19:56 ` Arnd Bergmann
2015-10-02 20:53   ` Mason
2015-10-02 21:11     ` Arnd Bergmann
2015-10-02 21:57       ` Mason
2015-10-02 22:12         ` Arnd Bergmann
2015-10-05 16:25           ` [PATCH v2] arm-soc: Add support for Sigma Designs Tango4 Marc Gonzalez
2015-10-06 15:57             ` [PATCH v3] " Marc Gonzalez
2015-10-09 13:18               ` Arnd Bergmann
2015-10-09 13:30                 ` Marc Gonzalez
2015-10-09 14:40                 ` Måns Rullgård
2015-10-09 19:01                 ` Mason
2015-10-09 20:24                   ` Måns Rullgård
2015-10-09 21:12                     ` Mason
2015-10-09 14:08               ` Rob Herring
2015-10-09 14:16                 ` Marc Gonzalez
2015-10-09 14:48                   ` Rob Herring
2015-10-13 15:54                 ` Marc Gonzalez
2015-10-13 17:55                   ` Rob Herring
2015-10-19 11:09                     ` Marc Gonzalez [this message]
2015-10-19 16:39                       ` Rob Herring
2015-10-19 17:32                         ` Mark Rutland
2015-10-20  9:20                           ` Marc Gonzalez
2015-10-20  9:50                         ` Marc Gonzalez
2015-10-20 10:04                           ` Russell King - ARM Linux
2015-10-20 10:54                             ` Marc Gonzalez
2015-10-09 14:12             ` [PATCH v2] " Rob Herring

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