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From: marc_gonzalez@sigmadesigns•com (Marc Gonzalez)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v3] arm-soc: Add support for Sigma Designs Tango4
Date: Tue, 20 Oct 2015 11:20:18 +0200	[thread overview]
Message-ID: <56260752.7030200@sigmadesigns.com> (raw)
In-Reply-To: <20151019173235.GF29001@leverpostej>

On 19/10/2015 19:32, Mark Rutland wrote:

> Marc Gonzalez wrote:
>
>> Found "arm,cortex-a9-pmu" in arch/arm/kernel/perf_event_v7.c
>> Are the PMU registers available from non-secure mode, or is
>> TrustZone going to get in the way?
> 
> Judging by the access permissions tables in c12.9 of the ARM ARM (ARM DDI
> 0406C.c), they're always accessible from non-secure PL1 in the absence
> of the virtualization extensions.

Thanks for digging up the info.

One more thing is unclear about the PMU. While things like the TWD block
seem to have a well-defined IRQ number, when I look at other platforms'
DT pmu node, everyone seems to have a different IRQ setup. Why is that?

Some use GIC_SPI, some use GIC_PPI
Some list 1 interrupt, others 2, others 4
Some have 3 cells (as expected by the GIC), exynos4 only has 2 (interrupts = <2 2>, <3 2>;)
Some use IRQ_TYPE_EDGE_RISING, others use IRQ_TYPE_LEVEL_HIGH

My SoC documentation only states:
1.12.2 ARM core interrupt vector
ARM A9MP core has a 32-bit interrupt vector that drives the ARM interrupt controller (GIC).
Input vector is the following :
- bit[1:0]: 0 / Unused.
- bit[2]: cpu_block IRQ controller0.
- bit[3]: cpu_block IRQ controller1.
- bit[4]: cpu_block IRQ controller2.
- bit[7:5]: 0 / Unused.
- bit[11:8]: Core N cross trigger interface IRQ (Coresight component).
- bit[15:12]: Core N performance management unit IRQ (Coresight component) .
- bit[31:16]: 0 / Unused.

So I'm thinking I should use
- GIC_SPI
- interrupts 12 and 13 (should I list the other lines if no SoC has more than 2 cores?)
- no idea on edge vs level, I'm guessing level

So I should add

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	};

Does that look (likely to be) correct?

Regards.

  reply	other threads:[~2015-10-20  9:20 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-02 16:02 [PATCH] arm-soc: Add Sigma Designs Tango4 port Mason
2015-10-02 16:10 ` Måns Rullgård
2015-10-02 16:33   ` Mason
2015-10-02 16:55     ` Måns Rullgård
2015-10-02 18:00       ` Mason
2015-10-02 17:13     ` Russell King - ARM Linux
2015-10-02 18:09       ` Mason
2015-10-02 18:53         ` Russell King - ARM Linux
2015-10-02 19:25           ` Mason
2015-10-02 19:56 ` Arnd Bergmann
2015-10-02 20:53   ` Mason
2015-10-02 21:11     ` Arnd Bergmann
2015-10-02 21:57       ` Mason
2015-10-02 22:12         ` Arnd Bergmann
2015-10-05 16:25           ` [PATCH v2] arm-soc: Add support for Sigma Designs Tango4 Marc Gonzalez
2015-10-06 15:57             ` [PATCH v3] " Marc Gonzalez
2015-10-09 13:18               ` Arnd Bergmann
2015-10-09 13:30                 ` Marc Gonzalez
2015-10-09 14:40                 ` Måns Rullgård
2015-10-09 19:01                 ` Mason
2015-10-09 20:24                   ` Måns Rullgård
2015-10-09 21:12                     ` Mason
2015-10-09 14:08               ` Rob Herring
2015-10-09 14:16                 ` Marc Gonzalez
2015-10-09 14:48                   ` Rob Herring
2015-10-13 15:54                 ` Marc Gonzalez
2015-10-13 17:55                   ` Rob Herring
2015-10-19 11:09                     ` Marc Gonzalez
2015-10-19 16:39                       ` Rob Herring
2015-10-19 17:32                         ` Mark Rutland
2015-10-20  9:20                           ` Marc Gonzalez [this message]
2015-10-20  9:50                         ` Marc Gonzalez
2015-10-20 10:04                           ` Russell King - ARM Linux
2015-10-20 10:54                             ` Marc Gonzalez
2015-10-09 14:12             ` [PATCH v2] " Rob Herring

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